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TLV62084A: AND'ing multiple PG outputs and associated pull-up resistors required

Part Number: TLV62084A
Other Parts Discussed in Thread: TPS62825

Hi –

 We have a design where we are powering an SOC which itself has 5 voltage rails:

  1. 1.8V AON (Always On)
  2. 3.3V
  3. 1.8V
  4. 0.8V
  5. 0.65V

 At times, we may decide to disable #’s (2)-(5) to save power while leaving the 1.8V AON supply up.  Our SOC has a PWRGOOD input in its Always-ON (AON) section that will be used to determine when the SOC can be safely released from RESET after all the supplies are back up.

 For the 5 supplies, we are using the TLV62084A.  I’ve attached a simplified sketch of how these are wired in our schematic.  Though it seems a bit more complicated than need be, there are other parts of the system on the board that require this complexity.  The basic function of the supply is such that the 5V supply and the 1.8V Always On supplies will be powered up all the time.  But, the other downstream supplies will be enabled/disabled depending on demands of the SOC.

 We want to make sure we are using the PG pins properly in relationship to one another and our SOC.  In the datasheet, it states:

The PG terminal is an open drain output and is specified to sink typically up to 0.5 mA. The power good output requires a pull-up resistor which is recommended connecting to the device output.”

Because we have 4 of the supplies that are effectively AND-ing their PG outputs together to feed our SOC’s PWRGOOD input, we’re concerned by this recommendation.  Our intention, as seen in the diagram, is to add pull-ups to each of the PG outputs to the 1.8V Always-ON rail.  Because the drive capability of the PG output is 0.5 mA, we selected a 178 kΩ resistor for each.  And because of the guidance at this video:, we elected to have a physical AND gate tying them together.


Because all of these supplies are having their PG outputs AND’d together, we need to keep the PG logic-high output at the same level as the AND input and our SOC.  Therefore, we are not following the recommendation of tying the power-good output pull-up resistor to the device output.  Instead, we are tying the pull-ups to a common 1.8V supply and utilizing the open-drain aspect of the PG output.


Could you please review the diagram and let us know if this is wired properly and if you see any concerns with the PG output logic?


Are there any other provisions that would help make this solution more robust?


Thanks in advance!



  • Hello Tom,

    Thank you for reaching to us with your concerns.

    The advantage of connecting the PG pin to the output rail via pull-up resistor is that there will be no current flowing into the pull-up resistor if the rail is disabled. This reduces the current consumption of the system especially at standby mode. However, it is not necessarily mean that PG pin can be tied to any stable voltage as needed by the application. So, I don't see any concern with your schematic/block diagram and should work fine.

    By the way, you mentioned that you intend to disable rail #2 to #5 to save power in a particular conditions. However, I don't see away how those rails will be disabled  while 1.8V AON rail is still operational in the schematic/block diagram. Is there a part of the circuit missing?  

    Best regards,


  • Hi Excel -

    Thank you very much for your prompt response.  I'm glad to hear the configuration I've chosen is acceptable.  It makes sense for the standby mode why you'd not want to waste current through the resistor.

    Yes - I did omit a portion of the circuit for simplicity with regards to disabling rails #2 to #5.  In fact, within the area you've circled in blue there is an AND gate that ands the PG pin from the 1.8V_AON regulator with a shutdown signal from our SOC.  So if either the 1.8V AON does not release PG or if the SOC chooses to shutdown #2 to #5, the AND gate will disable the 3.3V regulator (#2).  This, in turn, will disable the downstream regulators (#3-#5) via the PG to EN paths for each.

    Hope that makes sense.

    Thanks again,


  • Hello Tom,

    I got it. The 3.3V rail is disabled if the PG pin of 1.8V_AON rail is Low, or the SoC wants to shutdown rails #2 to #5. 

    By the way, I think you can tie all the pull-up resistors of the PG pin of rails #2 to #5 on any of its output voltages. It will reduce the current consumption at standby mode because there will be current flowing on the pull-up resistor only when one of the #2 ~ #5 rails is enabled.

    Lastly, you may want to consider newer devices such as TPS62825 in current or future projects. See the datasheet link below for details.

    Best regards,