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TPS746-Q1: TPS74633PQWDRVRQ1 3.45v voltage output

Part Number: TPS746-Q1
Other Parts Discussed in Thread: TPS746EVM-009, TPS746

Hi, 

I am using TPS74633PQWDRVRQ1 in my design to supply a portable device as shown below. When the input voltage is from a LiPo battery (input voltage ~ 3.4-4.2v), the output voltage is ~3.3v. But when I supply from the VBUS (input voltage ~ 4.5-5v), the output is fixed at 3.45v. I was wondering what is going on here. 

Another issue is I am using a switch for the EN signal. The switch works fine and the output of the chip is 0v when EN is connected GND if the input voltage is from the battery. When the input voltage is from the VBUS, the chip produces output even if the EN signal was connected to GND, the output is 3.45v regardless of the EN signal. 

Thanks.

  • Hi Daryl, 

    Thank you for the patience, I apologize for the late response. 

    I am using TPS74633PQWDRVRQ1 in my design to supply a portable device as shown below. When the input voltage is from a LiPo battery (input voltage ~ 3.4-4.2v), the output voltage is ~3.3v. But when I supply from the VBUS (input voltage ~ 4.5-5v), the output is fixed at 3.45v. I was wondering what is going on here.

    When you use the VBUS, do you see 3.45V stay there, or after a certain time it regulates to 3.3V? It looks like for some reason the device is in Dropout mode. 

    Another issue is I am using a switch for the EN signal. The switch works fine and the output of the chip is 0v when EN is connected GND if the input voltage is from the battery. When the input voltage is from the VBUS, the chip produces output even if the EN signal was connected to GND, the output is 3.45v regardless of the EN signal. 

    Have you tried moving the switch so that the EN signal is closer to the IN and after the capacitor?  

    The Vhi for enable is 1V and Vlo for disable is 0.3V. Unless your capacitors are not fully discharged when you do your testing, this can be causing the issue, therefore, going into a dropout mode. From Data Sheet page 20 section 7.4.3:

    "When the device is in a steady dropout state (defined as when the device is in dropout, VIN < VOUT(NOM) + VDO, directly after being in a normal regulation state, but not during startup), the pass transistor is driven into the ohmic or triode region. When the input voltage returns to a value greater than or equal to the nominal output voltage plus the dropout voltage (VOUT(NOM) + VDO), the output voltage can overshoot for a short period of time while the device pulls the pass transistor back into the linear region."

    This is some strange behavior if you are not in dropout mode in any way. Let me try and see if I find some samples so I can test this in the Lab. I will try to get back to you as soon as possible. 

    Best, 

    Edgar Acosta

  • Hi Daryl, 

    I went to the Lab and tested TPS74601, which is the Adjustable version.

    I also used a DC power supply to power the device. Following is the schematic from the TPS746EVM-009 Evaluation Module:

    I changed Cin and Cout to match the ones from your schematic, and removed C5 as you do not have a CFF. In addition, EN has a jumper, which allows me to connect and disconnect EN pin to Vin or GND, acting as a switch. The PG pin can be grounded or left floating, for the simplicity, I left PG floating. 

    I tested the device from 3.3V to 5V with EN=GND and EN=VIN and I did not see any odd behavior. 

    Is it possible that you do an A-B-A swap? And/or remove the LDO from the board and test it by itself? 

    Best, 

    Edgar Acosta.

  • Hi, Edgar:

    When I use the VBUS, I get 3.45 fixed and it does not change with time. 

    Have you tried moving the switch so that the EN signal is closer to the IN and after the capacitor?  I don't get what you mean here. However, I measured the EN in both states, it is ~0v but the chip still produces 3.45v. Also, when the switch is connected to GND, the capacitor is completely disconnected from the EN signal.

    I also verified the VIN to be 4.5 and 5v in two testings, both setups produced 3.45v in Vout.

  • I did A-B-A swaps and tried 4 different boards, and they all have the same behavior. I also, soldered only this chip in a board to make sure nothing wrong with the other components and I had the same issue.

  • Hi Daryl, 

    Do you any other rails going to the output of the LDO, i.e a 5V rail? from what you describe it looks like there might be a leakage somewhere.

    I also, soldered only this chip in a board

    Did you soldered a new unit? Is this board the same layout, or is it a completely different board? 

    Is it possible that you can provide scope shots of Vin, Ven, Vout VBUS for GND and Vin=Ven scenarios?

    In addition, is it possible that you can test the TPS746 LDO without a board? Its ok if you do not use a Cout, Vout might not be as stable but it should be a quick turn on/off situation just to get a reading from the LDO.

    I would suggest using the TPS746 EVM board to do some testing and use it as a control unit. 

    Best, 

    Edgar Acosta

  • Hi, Edgar--

    I don't have an EVM. I three different boards of the same design. Then soldered only the chip without the other components of the device (which is the same as the bare chip?) all this was consistent 3.45v

    Also, if there was a leakage why does it work (both EN and Vout) fine when I supply from LiPo?

    Is it possible that you can provide scope shots of Vin, Ven, Vout VBUS for GND and Vin=Ven scenarios?

    Yes, I can take some scope shots later.

  • Do you any other rails going to the output of the LDO, i.e a 5V rail?

    I use only 3.3v in the whole design.

  • I don't have an EVM. I three different boards of the same design. Then soldered only the chip without the other components of the device (which is the same as the bare chip?)

    The reason I asked for the bare chip is to exclude the board completely. From your schematic, Vbus and Vbat are not the same line:

    you are providing VBUS to the gate of the P-FET and VBAT to the Drain. 

    Unless there is a trace that is creating this leakage in the board from the FET to the LDO when you supply VBUS, that is why I am asking if you can test the LDO without a board and see if it still behaves the same. 

    Best, 

    Edgar Acosta

  • Okay, thanks for the elaboration. When you say leakage from FET to LDO, what part exactly do you think might cause this (which signal?). I can check the resistance between the traces that might be causing this.

    Also, I tested with the FET removed, and tested with FET replaced with another Zener and both resulted in 3.45v.

    Thanks,

    Daryl

  • Hey Daryl, 

    From a Schematic point of view it looks ok. I have shown the circuit to other engineers and agree, however, it was pointed out that there is a FB pin in your schematic, are you using the fixed version or the adjustable?  

    Is it possible that you can share your PCB layout? Are you using 1 layer or 2 layers? 

    Are all your GNDs connected together?

    Check the VBUS line and see if there is no short to other parts in the system, as this is were you see the issue. 

    If the GND is not the same for the VBUS and the EN, this could be causing some floating point, although this is very unlikely. 

    Since you replaced the PMOS with a diode and still see this behavior, check continuity from the Gate to Source line and see if there is a short when EN is to GND. 

    Best, 

    Edgar Acosta

  • From a Schematic point of view it looks ok. I have shown the circuit to other engineers and agree, however, it was pointed out that there is a FB pin in your schematic, are you using the fixed version or the adjustable?  

    The FB is NA, I am using a fixed version.

    Is it possible that you can share your PCB layout? Are you using 1 layer or 2 layers? 

    4 layer internal layers are for 3.3v and GND

    Are all your GNDs connected together?

    Yes, tested everything now.

    Since you replaced the PMOS with a diode and still see this behavior, check continuity from the Gate to Source line and see if there is a short when EN is to GND. 

    I removed the FET altogether (as it only passes VBAT) and I have the same issue.

  • Hey Daryl, 

    Thank you for sharing the image of the layout. 

    4 layer internal layers are for 3.3v and GND

    Just to confirm, GND is present in all 4 layers as well, or just one GND plane? 

    Is it possible that you send the actual files so I can examine it better, it looks like the VBUS is a big plane and it might be interfering with other things. 

    Were you able to test the LDO by itself, this will help a lot to determine if there is a possible leakage in the board or the LDO is not regulating properly. 

    Best, 

    Edgar Acosta

  • Hi, Edgar:

    I could not test it as I don't have an eval module. 

    Is there a way to send you the files privately?

    Thanks.

  • Just to confirm, GND is present in all 4 layers as well, or just one GND plane? 

    Yes 

  • Hi Daryl, 

    I could not test it as I don't have an eval module.

    I understand, let me go through the files and see what I can find. 

    Is there a way to send you the files privately?

    Sure thing, I just sent you a friend request, please accept so we can have a temporary private message session.

    Best, 

    Edgar Acosta