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TPS40210: PMP6963 - TPS40210 -TPS40211 - flyback operation with alternate reference devices

Part Number: TPS40210
Other Parts Discussed in Thread: TPS40211, TL431

I would like to be able to use a circuit similar to PMP6963 with both the TPS40210 and TPS40211 devices.  I understand there will need to be changes to the feedback\compensation passive components to make this work but I can't find any references as to how these values were developed for the PMP6963 design.  I know this design is made around the 700mV reference inside the TPS40210 I would also like to get passive component values which will let me use the 260mV reference device, TPS40211.  Thank you for your assistance.

  • Hello Natan,

    Please have a look at the power stage designer https://www.ti.com/design-resources/design-tools-simulation/power-stage-designer.html

    In this tool after you selected the flyback converter and entered your parameters, the loop designer helps to optimize the compensation components.

    Best regards,
    Brigitte

  • Hi Natan,

    i can not say for sure which tool the designer of the PMP6963 has used but i assume it was first calculated with the power stage desinger:

    Power Stage Designer | Overview | Design Resources | TI.com

    and finally optimized on the real design which is in general a good practice to get all the parasitic also considered.

    There is a good documentation about compensation here:

    https://www.ti.com/seclit/ml/slup340/slup340.pdf

    Best regards,

     Stefan

  • The tool as well as the document don't really specify any compensation changes required for differing voltage references.  In fact this diagram in the document seems to say any reference level should work since the opto is biased with the internal amplifier?

    At the core of the issue is at the moment we have a known working design using a TPS40210.  We remove the device from the board and put in a TPS40211 device and I get no switching but I do get a voltage from the internal LDO (VBP).  Are there some other considerations for the TPS40211 other than the reference level that I should be taking into account here?

  • Natan,

    The best option is to use Power Stage Designer 4.0 available on the TI website. Simply click the Flyback topology and then select the Loop Calculator bar at the top. Then in the lower left, select CCM Flyback and Type II isolated (w/zener) for the Comp Network. If you click the "COMP Network" button in the lower right, it will show you the circuit. Keep these thing in mind when using this tool:

    -  The "zener" eliminates the inner loop, greatly simplifying the compensation by eliminating the feedback path from Vout to the opto coupler.  

    -  PMP6963 uses this method, but there is also the internal error amp in the TPS40210 that adds gain (30k/10K = 3 = 9.5dB to the total loop). It also adds a fpole = 30k and 27pF = 200KHz, but this is very high and for noise filtering only.  

  • Thank you for the detailed explanation.  It appears like the vref change between the TPS40210 and TPS40211 devices isn't even part of the calculation with Power Stage Designer 4.0 for a flyback/type II isolated(w/zener).  In your opinion should there need to be a change in the compensation values when changing between the TPS40210 and TPS40211 devices?

  • The Vref difference between the TPS40210 and the TPS40211 should not make a difference. BUT, when setting the output voltage resistor divider on an existing stable design, you should only change the lower resistor value to (re)adjust the output voltage. This is because the top resistor is also part of the compensation network and effects stability, whereas the lower resistor does not.

    Additionally, the current sense resistor value also has an impact on the closed loop gain when designing the power stage. The lower the current sense resistor value, the higher the loop gain becomes. For example, if its value were lowered from 0.015 ohms to 0.005 ohms (in an existing stable design), the effective loop gain increases by 0.015/0.005 = 3X => +9.5dB. This would push the bandwidth higher and could lead to low phase margin and instability. An easy was to correct for this is to then lower Rcomp by 3X, increase Ccomp by 3X (this leaves the compensation zero the same) and increase CHF (high freq comp cap) by 3X.

  • Thank you for the additional information, I am a bit stuck then.  My design isn't exactly PMP6963 but is almost exactly like PMP7132, which for some reason has been deleted from the site?  All I have done is swapped the TPS40210 with the TPS40211.  I am getting no switching but read 8.2V on VBP and .26 on COMP.  Which seem like sane values,  do you have any more ideas for troubleshooting?  This design has been in production for years with the TPS40210 for us, just trying to be able to get a 2nd device we can use during the chip shortage now.

    slur949.pdf

  • Natan,

    If the COMP voltage is 0.26V, that is too low and will prevent the PWM from starting. It must be higher than this (assuming the output voltage is 0V).

    I believe the issue you are seeing with the 40211 is due to the internal 0.26V reference and the gain set by the two resistors between the COMP and FB and FB and the opto. The gain from COMP to opto (pin 3) is Vcomp = -Vi*Rf/Ri + Vref*(1+Rf/Ri) = -Vi*3 + Vref*4. Try plotting this in excel. With the 40210, the Vref is 0.7V so the gain of the internal E/A is different than when you switch to the 40211. With Vref=0.7, the resistors values are set so that the COMP output voltage can swing from 0V (zero PWM) to ~3V (100% PWM) for an input voltage (opto pin 3 voltage) between 1V and 0V. If you change controllers (Vref = 0.26V), the COMP voltage can only go as high as 1V (not 3V any more), which is not high enough to get the PWM to start. Remember a high COMP voltage = high PWM. So, try changing the feedback resistor from 10K to 34K if using the 40211. This will increase the feedback gain from 3 to ~10, and should allow the COMP voltage to reach as high as ~3V to get 100% PWM. BUT, this higher gain also means that the full swing voltage at the opto pin 3 will decrease from 1V to 0.3V. I believe that this change will increase the loop gain, so recompensation (around the TL431) may be necessary. Try this change and see if is the converter starts switching.

    Vi Vr Rf Ri Vcomp Vi Vr Rf Ri Vcomp
    0 0.7 10000 3320 2.81 0 0.26 34000 3320 2.92
    0.1 0.7 10000 3320 2.51 0.1 0.26 34000 3320 1.90
    0.2 0.7 10000 3320 2.21 0.2 0.26 34000 3320 0.87
    0.3 0.7 10000 3320 1.90 0.3 0.26 34000 3320 -0.15
    0.4 0.7 10000 3320 1.60
    0.5 0.7 10000 3320 1.30
    0.6 0.7 10000 3320 1.00
    0.7 0.7 10000 3320 0.70
    0.8 0.7 10000 3320 0.40
    0.9 0.7 10000 3320 0.10
    1 0.7 10000 3320 -0.20

       

  • Thank you for that very thorough answer.  Your idea of increasing the gain to 10 did indeed get my device switching, and it is now outputting the appropriate voltages again.  I now understand how this circuit works a bit better.  Does the value of the shunt R on pin3 of the opto matter, looks like it's ratio relates to the series R to the diode on the opto?  I will play around with the Power Stage Designer a bit to see what compensation changes I might want to make.

  • So here are my calculations based off the following parts and system requirements:

    T = 750313102
    D = SBR40U300CTB
    Q = BSC123N08NS3
    Opto = TCMT1107

  • Natan,

    Good to hear the output voltage is regulating now. I do not believe the res value (1K) from the opto to GND should not make a difference in the gain.

    In your design there is a RHPZ at ~15KHz, so you should set you expectations for the converters BW to ~1/5 of this max. You cannot have a stable PS that approaches the RHPZ. I would say to try to get 1K - 4KHz BW with >45 degrees phase margin. The RHPZ frequency is lowest at max load and Vin minimum, so be sure to check it there.

    In the compensation data you posted, I noticed that the Rp/Rd ratio is very low at 0.032. In general, this should be as close to 1 as possible. Assuming you can increase this to 0.32, I attached a possible set of compensation values. The power stage pole at ~30Hz is now aligned with the zero of the compensation network (Rcomp and Ccomp). This has a huge impact on increasing the phase margin (yellow) at ~1.5KHz. Here the PM is about 60 degrees, which is good. 

  • I just want to clarify the Rp/Rd ratio refers to R27/R16 in PMP6963?

    If so I am working off of the original values in PMP7132 which used 1k and 30.9k resistors for Rp/Rd, see attachment in previous post for schematic. I will make this ratio 1 per PMP6963. Testing loaded and unloaded seems good so far with integrating your suggested changes.  Here is my current iteration of the schematic with your input:

  • Natan,

    Rp/Rd would be R26 / (R18+R15) which is on either side of the opto (see attached). So R26 does have an impact on gain of the entire loop gain, but not on the transfer function of the TPS4021x internal E/A (R17 and R24) I mentioned previously.

    Sorry, but to complicate it a bit more, but there is an additional pole formed by R26 and C25 (assuming R28 = 0, as in PMP6963) or a pole-zero combination when R28 is non-zero. These are not included in the comp network shown below, but still need to be accounted for. The explanation for R28-C25 gets rather complex but in short is necessary when using the Opto Network - "Type II isolated with Opto (w/ inner loop)". Unfortunately I don't know of any reference material to suggest for this, but the link below may help. The "goal" of C25 - R28 - R26 is to lower the gain of the inner loop. This is the nested inner loop due to R18 / R15 being connected directly to Vout. With the "zener" approach of PMP6963 that inner loop is removed and R28 is not necessary. For this reason, the zener approach can simplify the compensation considerably when selecting compensation values across for the TL431.

    https://www.eetimes.com/power-tips-compensating-isolated-power-supplies/

    If you would like to work with the 30.9K & 1K values from  PMP7132 (Rp/Rd = 0.032), that is fine, as that design has very good stability. Generally, I am used to seeing this ratio much smaller, but in this case it works. Just change the Rcomp and Ccomp (from my previous post) to get the BW to be in the 1KHz range. Keep in mind that PMP6963 uses the the "isolated opto w/ zener" compensation network whereas PMP7132 used the "isolated w/ inner loop" compensation network, which is why the Rp/Rd ratios are so different. The Rd value can be much lower (as well as the Rp/Rd ratio ) when a low voltage clamped (zener) voltage is used.

  • John,

    Just to pull this all together I want to make sure I have this correct:

    -Starting with my similar to PMP7132 design

    -Increase gain for error amplifier from 3 to 10

    -Change Chf/Ccomp/Rcomp to 1k optimized values

    Are you then comfortable with the values ending up in this schematic?

  • Hi Natan,

    I assume you have done the calculation with all the parameters from the Inductor and output capacitor network, so that you have placed your poles and zeros as shown in the calculation by provided by John.
    Basically this values are looking OK.

    Nevertheless i highly recommend to make some Bode Plots with the real board and optimize the compensation with that. As this always gives the real performance including board and device parasitics.

    Best regards,

     Stefan