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TPS3813: Timing

Part Number: TPS3813

I'm confused about the timing requirements for toggling WDI without causing a reset. I have WDT = 0V and WDR = 0V It looks like I need WDI to start out low for some long period of time. When I'm ready for NRESET to go high, I need to set WDI High for X ms. From the datasheet, The lower window frame is 6.27ms - 9.46ms. I think this means that WDI needs to be high for at least 6.27 ms. Question 1: Does WDI need to go low in the lower window? If so, how long does it need to be active for? Question 2: If WDI only needs to be active in the lower window, it looks like I can drive WDI low any time in the Window frame in the 190ms < 300ms following the initial 10ms? Question 3: What should the timing really look like? a) My current setup is driving low for 600mS (I expect this to force a reset) b) Kick the watchdog by setting WDI High for 10ms. c) Set WDI low for 200ms d) Repeat from step b I assume I should be able to loop on b-c indefinitely without tripping a reset.

  • Hi Matt,

    I am looking into this - I will get back to you shortly. 

    -Tony

  • Hi Matt,

    To your questions in the order that you asked them

    1. No
    2. WDI needs to transition in that window frame to prevent /RESET from asserting - if it transitions before 6.27ms since the last transition, then you cannot be sure whether /RESET will assert. See figure 7 over here from the datasheet: 
    3. You should be having some sort of square wave or pulse, where an edge occurs no sooner than 6.27ms since the last edge and no later than 200ms since the last edge. If you do trigger /RESET, then it will assert for 20ms-30ms (from section 7.7 in the datasheet). After that time, the reset will be released, the lower boundary will be disabled and after the first low-to-high transition is detected, the lower boundary will be enabled and we will enjoy this behavior until the circuit is powered off.

    Let me know if this answers your question.

    -Tony

  • Thank you for your explanation!