Other Parts Discussed in Thread: LP87524P-Q1
-Can you please confirm that the LP87524-Q1 (4 independant DCDC channels) can be used for this use case?
Voltage current (Abs max) Ambiant temperature : 60°C
+3,3 V +/-4% 1,9 A
+1,8 V +/-4% 0,8 A
+1,1 V +/-4% 1,3 A
+1,0 V +/-4% 0,9 A
Since the sum of the current is much below the 10A max are there some ways to optimize the design for this use case (like reducing amount/size of input capacitors or output capacitors)?
-The LP87524B/J/P-Q1 TRM UG - SNVU663A does give the Peak current limit (page 5 tab 3-1) that are programmed in the factory (OTP).
Does it means that at a given point in time:
the sum of all the Iout cannot not exceed 10A
the Iout of each DCDC rails cannot exceed this factory programmed limit (ex: ILIM0: 2.5A for DCDC0)
Can you confirm that the pre-programmed sequencing can be changed using I2C by reprogramming the DOUBLE_DELAY bit in CONFIG register and HALF_DELAY bit in PGOOD_CTRL2 register?
Thanks in advance!