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BQ76200: why bq76200 output looks locked?

Part Number: BQ76200
Other Parts Discussed in Thread: BQ4050, BQSTUDIO


We got an issue regarding bq76200 application. Please help and let me know why this happening and how to solve the issue:

We are using the output of bq4050 (pin 31 CHG/pin 28 DSG), then through resistor divider to reduce the control voltage, using the reduced control voltage to control bq76200 pin4 CHG_EN and pin6 DSG_EN,further to control bq76200 CHG/DSG output,  to drive charge and discharge MOSFETs on/off.

Through bqStudio, though there is no any protection happening, we can read both CHG and DSG bit on (red); I measured: B+ is 12.8V,  pin4 (CHG_EN) and pin6 (DSG_EN) of bq76200 are 2.8V, pin1(VDDCP) of bq76200 is around 22.3V, but pin16 (CHG) and pin12(DSG) of bq76200 are around 12.8V, not as expected around 22.3V. then both CHG and DSG FETs cannot be turned on properly.

If I send command through bqStudio, to disable FET_EN, bq4050 turns off both CHG/DSG,  then I manually to send command through bqStudio to turn on CHG FET, then DSG FET, at this time, I can get bq76200 output properly, both CHG and DSG FETs can be turned on.

Please be noted, during all this time, MCU is not involved.

Could you please help to check my schematic, and let me know why this happening and how to solve the issue?



  • Hi Joy,

    Common questions and issues with the BQ76200 are described in the application note  

    From your description the interface from the BQ4050 provides adequate voltage level for the BQ76200 enable inputs, 2.8V is a high level, and confirmed by the individual switching of the CHG and DSG.  What is likely happening is that with FET_EN set the BQ4050 turns on both CHG and DSG at the same time, this likely overloads the charge pump on the BQ76200 causing it to go to UVLO and turns off the drivers again.  Compare the result in your circuit with figures 4 and 5 of the application note. You do have a lot of capacitance on VDDCP, check to see if you may need to adjust the resistance to the gates of the FETs or add the 100 ohm and 18V zener between DSG and PACK pins to avoid switching losses.  Also check the filter capacitor on the PACK pin, it should generally be 10 nF or smaller.