What is the minimum required dead-time? This question was asked in a related thread, and the answer was to look at this app note:
https://www.ti.com/lit/an/snva815/snva815.pdf
But that page gives an error. Perhaps it was removed or renamed? Please advise where one might find this information.
I understand the answer is likely "it depends" but I'm looking for ball-park numbers assuming some maximum SW node capacitance...
...perhaps it should be >8ns since the delay matching is a maximum of 8ns (see datasheeet screen grab below)? I'm not exactly sure what that delay matching is telling me, so apologies if this is a dumb question, but it'd be great if that could be explained more clearly. A timing diagram would be fantastic...
Thanks,
Ryan
