One common practice when people are using an e-load to mimic a resistive load is to use the e-load in constant current mode. However, by doing so the user will often experience unwanted device shutdowns. Why is this happening?
Resistive loads in nature will always have current proportional to the voltage applied across it by the factor of its resistance. During the high side switch FET turn-on period, the voltage across the FET Vds ramps down (on the other hand, the voltage across the resistor will be ramping up), and the current through the FET ramps up. The IV overlap loss across the FET will be the integral of the voltage Vds and current Id.
In the case of e-load in constant current mode, the e-load will have a closed loop system where it always wants to draw the preset current. This will lower the resistance during FET turn-on process, which makes Id much larger from time periods t2 to t3. This can cause extra power loss as the area under the integration curve would be larger and cause thermal shutdown during the initial power on phase.
To mimic the actual resistive load using e-load, please use it in constant resistance mode to avoid unwanted behavior of the high side switches.
