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BQ76PL455A-Q1: BQ76PL455A-Q1 Cell balancing getting off.

Aniket Bagade
Prodigy 200 points
Part Number: BQ76PL455A-Q1
Other Parts Discussed in Thread: BQ76PL455A,

Dear Team,

I am trying to balance single cell using BQ76PL455A,But after 1 hour balancing getting off automatically.  I also configure register CBCONFIG 0x13 (19) Balance Configuration with value 0x08 but i am getting same issue. Could you tell what might go wrong?

Regards,

Aniket.

  • 0
    TI__Genius 14890 points

    Hello Aniket,

    Please try setting the CBCONFIG register to 0x00 (no timeout) and see if it stops. If it does, then that means we are probably seeing a fault. More details about cell balancing are copied below:

    Sixteen internal drivers control individual cell balancing through the pins labeled EQ1…EQ16. When the device issues a balance command through register CBENBL, the bq76PL455A-Q1 asserts the EQ(N) output, switches to the VSENSE(N) rail and turns on QBAL. With a de-asserted register bit, the EQn bit switches to the VSENSEn–1 rail, turns off QBAL, and reduces the balancing current to zero. The squeeze (OWD) function must be disabled for correct balancing operation by setting TSTCONFIG[EQ_SQUEEZE_EN] = 0.

    If CBCONFIG[BAL_CONTINUE] is set to '0', then when there is a FAULT the bq76PL455A-Q1 disables balancing. The CBENBL register bits clear to indicate this event. However, there is one exception. The USER checksum fault indicated by FALUT_DEV[USER_CKSUM_FLT] does not disable balancing. The following describes the scenarios:

    • BAL_CONTINUE = 0: CBENBL is set to 0 and balancing is disabled until the fault and fault status bits are cleared. Information about what was being balanced is discarded. No change is made to the BAL_TIME bits in CBCONFIG. The CBENBL register must then be rewritten with the desired balancing action.

    • BAL_CONTINUE = 1: There is no effect on CBENBL and CBCONFIG and any balancing in progress continues.

    Changing the CBENBL register will create a checksum fault and cause FAULT_DEV[USER_CKSUM_ERR] to be set. This may be a result of setting bits to enable balancing for cells, or the register being reset, because of a fault or CBTIME expiring.