TPSM82823: Max Output Capacitance

Hi Steve,

In my opinion, we need to make sure that the effective output capacitance is within the recommended values stated in the datasheet – regardless of how far the caps are placed in the layout.

In this case, the best way alternative would be to use a device with an external compensation network such as the TPS54x18 series of devices (like the TPS54218). However the solution size will be much larger.

Regards,

Febin

Thanks for the reply. I checked out the TPS54218 on WEBBENCH and the max recommended capacitance is 100uF. One of my FPGA rails has 800uF on it. I've tried many devices on WEBBENCH and tried modifying the output capacitance to 800uF, but I've yet to find a device where this is in the recommended range. Can you recommend a device I could try for this? It would be great if maximum recommended output capacitance was a searchable parameter, it would save a great deal of time.

Hi Steve,

Unfortunately, we do not have a Low Voltage Low Current Buck converter in our current Portfolio that can support such large Cout. 

Also, our search tool does not support Cout as a search parameter.

Nevertheless, I will look further into what could be the best alternative in this case. Meanwhile could you please share more details like the FPGA used, End Equipment, Vout/Iout requirements, etc.

Regards,

Febin

The FPGA is Xilinx Artix 7 XC7A200T, so by no means a  large and powerful one. For the capacitors required see

https://www.xilinx.com/support/documentation/user_guides/ug483_7Series_PCB.pdf

The 1V rail includes VCCINT & VCCBRAM. See page 16. Around 800uF required. Its 1V +/-50mV total error. Initially the design requires less than 1A, but as more signal processing is added then this will increase. If the FPGA is fully utilized, then 6A may be required. The project is a 6 channel synchronous  long acquisition digitizer with signal processing. I've looked at many devices including the EN63A0QI (not currently available, like a lot of parts) but in its datasheet it specifies a range for the output capacitance within the feedback loop, but then states that a much larger amount of bulk capacitance can be added outside of the feedback loop. With the required output capacitance stated for the Texas parts, would that all be required to be inside the feedback loop? It is certainly impossible to include all the the FPGAs  distributed capacitance inside the feedback loop of the controller. Seeing as many people obviously find solutions for similar problems to mine, then I might assume that they have a precise of capacitance inside the feedback loop and a arbitrary amount of bulk capacitance outside it. Or maybe all the suitable parts are out of stock.

Hi Steve,

According to me, the best alternative would be again the TPS54x18 family. Devices with external compensation have more flexibility and can support large Cout. I looked through the d/s of TPS54218 and did not find any max Cout mentioned, which means it could support large Cout. I am not sure how you designed this on Webench, but I propose to follow the d/s step by step for designing according to your system needs. And then input these values in Webench.

What I also advise is to have the loop stability or transient measurements done on the final BOM. In the past we have seen TPS54x18 in similar applications. Therefore, if the control loop is stable with the distributed capacitance, then I don't see a problem with such implementations. 

Regards,

Febin