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LMZ30606: output voltage abnormal

Part Number: LMZ30606
Other Parts Discussed in Thread: TPSM82480

Hi, expert,

My customer found there are two steps of LMZ30606's output. Could you please help analysis the reason? Thanks.

C1132 and C1138 are DNP. 

The green curve is output voltage which has two steps, and the yellow curve is INH/UVLO signal.

Best Regards.

Chen

  • Hello Chen,

    Could you ask customer to capture the VIN and PH waveform on the same image as well as INH/UVLO and VOUT like shown before ?

    Is customer powering several stages on their board during powerup ? It may be that the output voltage is driven by the output during their tests.

    I recommend customer to have a look at the following App note: https://www.ti.com/lit/an/slyt689/slyt689.pdf?ts=1627993184964

    Do you know why customer is not following our datasheet recommendation for R_RT & R_SET values ?

    Value used by customer is 1 MOhm.

    Do you know how much output cap customer is using here ? I see 4 output caps but image is cut on the right-hand side.

    Does customer know the newer, smaller and cheaper TPSM82480 ? I also would suggest your customer to have a look at it. 

    Let me know once you get feedback from customer or if you have any further questions.

    Thanks a lot!

    Regards,
    Dorian 

  • Hi, Dorian

    Please see below pics, the yellow one is VIN and the green one is PH.

    Yes they are powering several power rails like 0.9V, 1.03V, 1.8V and 3.3V of FPGA.

    They set Rrt to 1.2MOhms to set the synchronization frequency.

    And the output capacitors are enough.

    Best Regards

    Chen

  • Hello Chen,

    As you can see on the PH green waveform, the output voltage starts increasing before any switching occurs (before device is inhibited) from LMZ30606.

    I have the feeling that the load is influencing the output before regulation.

    Could you ask customer to unsolder B64/B65 and see how does the output look like at startup ?

    If startup looks like typical startup shown in Figure 24 of datasheet, the behavior would be driven by internal circuits of the FPGA.

    Let me know if you have any questions.

    Thanks a lot!

    Regards,

    Dorian 

  • Hello Chen,

    Do you have any updates here ? 

    Was customer able to look at startup behavior with B64/B65 unsolder ?

    Let me know if you have any more questions or comments.

    Thanks a lot!

    Regards,
    Dorian 

  • Hello Chen,

    Due to inactivity, I will close this thread.

    If you have any further questions or would like to re-open the thread, please reply below.

    Thanks a lot!

    Regards,
    Dorian