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BQ76952: REG1&2 , DIO & TIDA-010208

RP
Prodigy 70 points
Part Number: BQ76952
Other Parts Discussed in Thread: TIDA-010208

Hello,

My design is in the final stage for the release and a brief about the design is available below.

Cell configuration: 4S to 16S (Configurable)

Cell Chemistry: LFP and NMC

Operation: Standalone and Host Control

MCU is supplied with 5V and 5V IO's.

Maintained similar auxiliary power strategy used as in TIDA-010208 except LDO section.

Need clarification on below points:

  • Both REG1 and REG2 configured to 5V. REG2 is to power up MCU during standby and shipping mode (Similar to TIDA-010208). Will there be any issue at low BAT voltage (10V) in 4S configuration using both regulator output as 5V?
  • REG1 is configured to 5V and as per datasheet DIO's refer REG1 output.In the datasheet (7.6 Digital IO) output logic levels are specified w.r to VREG1, where as input logic levels are specified w.r to Vreg_1v8. Are these digital inputs are 1.8V logic only? Need this data to verify the compatibility with a 5V IO MCU.
  • Planned to use HDQ and DCHG lines as temperature sensing lines.Will these lines refer to 1.8V supply or 5V(Vreg1 configured to 5v)?
  • Whether is it possible to configure individual digital IO on AFE to any power supply or is there inter dependency on other IO's and functions?
  • What would be the supply current of AFE in normal mode where RGE1=REG2=5V,CHG= ON in 11V overdrive mode, DSG = ON in 11V overdrive mode condition?
  • Is it possible to configure REG1 as 5V alone and share the same supply with MCU by avoiding REG2 OFF?
  • What is the maximum battery voltage used in TIDA-010208?
  • What is the function of 0.1uF capacitors across the MOSFET'S in mosfet paralleling section in TIDA-010208?
  • What is the purpose of reverse bias diode across Pack+ and Pack- terminals?
  • Why Q29 is rated for 60V only?

Regards,

Ravi

  • 0
    TI__Guru 54715 points

    Hi Ravi,

    1. There should not be an issue using REG1 & REG2 with a BAT of 10V.  Note in the https://www.ti.com/document-viewer/BQ76952/datasheet/GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000229480#GUID-XXXXXXXX-SF0L-XXXX-XXXX-000000229480 section adding the headroom to the BREG would require about 8V or greater.  Be sure the external transistor is not starved for current.
    2. .Yes, input level thresholds are at the 1.8V supply references shown, but can go up to 5.5V for high.  When driving a low to the MCU output should be able to go low, lower than commonly required for 5V CMOS logic. 
    3. When configured as temperature inputs the multifunction pins are pulled to REG18 and have that limit.  They do not relate to the VREG1 or VREG2 setting.  Since they are multifunction pins be sure to see the conditions and settings which apply to the selected mode.  See the technical reference manual sections 13.3.2.15 Settings:Configuration:HDQ Pin Config and  13.3.2.16 Settings:Configuration:DCHG Pin Config
    4. Each configurable IO can be selected for its drive level, typically REG18 output or REG1 output.  REG18 should not be expected to source much current. Check the technical reference manual for the pin of interest.
    5.  The conditions you list are not specifically characterized. The 286 uA typical in the data sheet is an average value, peaks will be higher and current may change with operation.  REG2 enabled should not draw significantly more current.  The charge pump will have a current gain from the load to BAT of about 20, adding 1 uA of load to the FET outputs will add about 20 uA operating current.  Load for the regulators will come from the external transistor but BAT will see some increase due to the base current of the transistor. If your transistor has a gain of 100 and you are using 50 mA expect the BAT current to increase about 500 uA.
    6. Yes, if the load is in the range of the regulator only 1 regulator needs to be used.
    7. The TIDA-010208 author did not specifically list the voltages used for each test.  The design guide indicates a 48V nominal battery in several locations, and some scope waveforms show 48V.  Since the COV threshold is set at 4200 mV in table 2-1 the board should be able to reach 62V without fault when configured as described.
    8. A pair of series 0.1 uF capacitors is used for an ESD path between  the PACK terminals and across the FETs.  If the FETs are off these provide a path for ESD current around the MOSFETs. 2 are used in series so that if one fails short the other is still available.  Mounting these at 90 degrees from each other may avoid both failing from board flex, it is not always done on our EVMs.
    9. The reverse bias diode is a flyback diode, if the discharge FET opens with an inductive load it will limit the excursion of PACK+ below PACK-. Note that D47 will prevent Q29 from operating unless D47 opens.
    10. Q29 will see only the VGS voltage of the power FETs, typically the 11V from the charge pump.  In transient D39 may conduct raising the Q29 VDS voltage to about 16V.