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UCC21750QDWEVM-025: Turn-off time during desaturation event query

Part Number: UCC21750QDWEVM-025
Other Parts Discussed in Thread: UCC21750, , UCC21710

We are using your UCC21750QDWEVM-025 evaluation board to determine the feasibility of the UCC21750 for our application and have some questions.
(1) Figure 14 in your SLUUBX2B user's guide shows the short circuit waveform. Why does it take 2.5us to turn-off when your datasheet indicates several hundred nanoseconds at worst case? The only difference I can see between the two cases is that the datasheet specifies a load of 100pF where as the evaluation board is 10nF.

(2) Our requirement is a turn-off time of less than 1.3us. How do we achieve this with the UCC21750? The desat capacitance in the evaluation board is 27pF (plus the capacitance of the Schottky and Zener diodes D8 and D7 respectively). How can we meet our requirements if the desat capacitance is already very low?

(3) I have conducted an experiment with the UCC21750QDWEVM-025 to replicate the waveform of Figure 14. I am observing similar turn-off times however, I am observing the desat threshold exceeding the 10V maximum specified in the datasheet. In fact, it appears to be over 11V. Are you able to comment on this?

Yellow = Input signal (IN+)
Green = Gate signal (GATE)
Orange = Desat pin (pin 2 of UCC21750)
Blue = Fault pin (FLT)

  • Hi Antonios,

    For more details on the DESAT pin timing refer to Figure 40 in the datasheet.

    To answer 1 and 3:

    When the gate turns ON there's a leading edge blanking time on the DESAT pin during which the internal current source to charge the blanking capacitor is OFF. This is the parameter t_DESATLEB in the datasheet (200ns typical).

    After this time the 500uA current source is enabled to charge the blanking capacitor. The timing it takes to charge the blanking capacitor is dependent on the charging current, blanking capacitor, and the capacitance of the trace and other components on the node. On the EVM that gives us a blanking time of about  ~1.5us. To reduce the blanking time you can increase the charging current with the use of an external resistor and a power rail on the secondary like the same power rail used for VDD or by connecting to OUTH.

    After the DESAT voltage reaches the 9V threshold the voltage on the DESAT pin will have to remain >9V for longer than the DESAT de-glitch filter. This parameter is t_DESATFIL in the datasheet (140ns typical). During this time the internal current source is still active which will continue to increase the voltage on the DESAT pin. That is what you captured in your waveform. 

    After the DESAT de-glitch filter the gate driver will shutdown the current source and will begin soft turn OFF which will discharge the gate with a set 400mA soft turn-off current. The 400mA current will discharge the gate until the gate voltage reaches VEE+2V. At that point the miller clamp will bring down the voltage on the gate down to the VEE voltage.

    Note: For SiC or IGBT the switch will turn off and stop conducting current when the gate voltage drops lower than the gate threshold voltage. For SiC it is recommended for the short circuit current to be detected and shutdown within 1us (drain current from 0A back down to 0A). 

    To answer 2:

    As mentioned above to reduce the blanking time without further reducing the blanking cap you can add a resistor from VDD to the DESAT pin to increase the charging current.

    Another option would be to look into the UCC21710 driver. The only difference between the UCC21710 and UCC21750 is the short circuit detection pins. The UCC21710 has the OC-pin  which is only made up of a comparator and does not have an internal current source. This pin can be used to measure the voltage drop across a shunt resistor, although it can also be configured to detect a desaturation event like the UCC21750 with the help of some additional external components. The additional components include a resistor divider network and current source created with a resistor connection to VDD or OUTH. The advantage of the OC-pin is that it allows more flexibility on the VDS detection voltage and timing. Please refer to the calculator tool found in any of the UCC217xx family product folders to help with quick calculations for this DESAT using OC- pin configuration.


    Let me know if there's any additional questions or further clarification.

    Best regards,

    Andy Robles

  • Andy,
    Thank you for your detailed response.

    After adding the exact desat components in my simulation as what's on the evaluation board, there is very good correlation with the timings. I have placed a 15k resistor between VDD and DESAT (as per suggestion) in my simulation and the turn-off time is now less than 1us. I will add a resistor on the evaluation board next time I'm in the office and compare the timing.
    (1) What is the criteria in selecting this resistance value? Is there any documentation that you can suggest to guide me in selecting an appropriate resistor value?

  • Antonios, 

    Andy is Out of office for a bit, so I will help here. 

    The calculation for the additional resistor is different than what we do for a UCC217xx variant that has OC pin and NOT desat, since DESAT provides a fixed charging current which OC pin versions dont have. 

    I am attaching a short report which shows how the DESAT-to-VDD resistor value can be calculated. 


    Please let me know if you have any further questions. If this answers your question, please let me know by pressing the green button.