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TPS54519: Layout for AGND and GND

Part Number: TPS54519
Other Parts Discussed in Thread: TPS568230EVM, TPS62867, TPS568230


I have a question on TPS54519 layout. From my previous experience, AGND of IC should be connected on single point with GND (PGND) to prevent switching noise conducting from GND (PGND) to AGND. But TPS54519 datasheet shows GND and AGND are tied together. Is it not causing a switching noise injection problem?

My previous knowledge is as shown below. ANGD is connected to GND plane (layer 2) thru a via.

<TPS568230EVM top layer layout>

  • Hi Ella,

    Both ways are true on the TPS54519 layout.  You can see that all the analog signals are first tied together and then they tie to the AGND pin.  Then, this AGND ties to PGND and the thermal pad, which are all basically in the same place.  This is correct.

    For new designs, I would recommend using a newer IC such as the TPS62867.



  • Hi Chris,

    You can see that all the analog signals are first tied together and then they tie to the AGND pin.  Then, this AGND ties to PGND and the thermal pad, which are all basically in the same place.

    Got it. Thank you for your comments. But one thing is still confusing for me. TPS54519 has AGND and PGND tied together directly on Thermal pad. But to my knowledge, PGND is connected to the thermal pad but AGND should not be connected to the thermal pad, to avoid switching noise coupling to AGND from PGND. (Please find TPS568230 as an example) AGND should be an island that connects to PGND thru a single short trace or 0ohm resistor. Is there any structural difference on thermal pad of TPS54519 and TPS568230 (or other devices)?

  • Hi Ella,

    Every IC is a little different.  The GND pin location on the IC is very different for these 2 devices, for example.

    Let me loop in support for the TPS568230 to explain its layout.


  • Thanks Chris,

    Let me clarify my question for you and someone who would jump in for TPS568230 support.

    Q1 (TPS54519).

    Why is the narrow trace of AGND recommended as shown in the layout example? I used to think that it is to separate Power GND and Analog GND for noise decoupling but AGND pin is directly connected to GND pins at thermal pad and wide GND plane. If there's switching noise on the GND, that would directly conduct to AGND thru those connection. Then what's the purpose of the narrow separated trace of AGND?

    Q2 (TPS568230).

    Unlike TPS54519, TPS568230 recommends AGND pin (pin 13) is not connected to thermal pad (according to EVM layout). Those are monolithic IC so I believe there should be only one ground level. But the ground layout recommendation is different. Could you help me to understand what the difference of two ICs is and what the best layout practice for thermal pad, GND pin, and AGND pin?

  • Hi Ella,

    I understood your question here. 

    I will check with TPS54519 design and feedback to you on Monday US time. Please kindly wait.



  • Regarding the TPS54519


    There must be a connection from AGND to GND.   A single point connection is best.  But there other connections that may work.


    On the EVM sensitive analog components are all tied to an AGND plane and connect to the ground plane on second layer with a via.   The converter high currents flow into the device GND pins (red lines)and the AGND pin connects to the GND here.

    A better connection for AGND could be to via connect to the thermal pad near the SW node pins.   But to connect AGND there would need a via, a trace that would break the contiguous copper pour on second layer (possibly affect thermal performance), and placing AGND near SW node is probably not a good idea, if sw noise couples to agnd.

    On the evm the AGND copper pour connects to the GND with a via on second layer.  A better connection for AGND could be a trace (isolated from pour) to the  4 vias, if the device was higher output current

    But the high current path (red line) on second layer is far away  AGND connection with via (blue)


    So EVM layout is good, there are  some changes could be made (pink)

    Connect AGND to pin on top layer and use trace to connect AGND to GND rather than a pour.







  • Hi David,

    After reading thorough your comments, I just want to clarify : 

    GND pin and AGND pin can meet at power pad under the IC as noted in datasheet below, but not meeting at power pad is also okay only if they have connection far from the device. Could you kindly confirm if my understanding is correct.

  • This seminar paper discuss in depth the grounding in the dc/dc converter layouts.

    Following the datasheet layout is recommended. but there are other layouts that can work.   

    The goal is to separate noisy from quiet.     The sensitive components must have a common AGND and connect at one point to PGND.

    A bad layout for the TPS54519 would be connecting the sensitive components AGNDs directly to the PGND (red line).

    The high current flowing across the plane would cause different voltages on the sensitive components.   

  • Your comments help a lot to understand the overall layout practice. Thank you for your great help.

  • Hi Ella,

    Thanks for confirmation.