Other Parts Discussed in Thread: TLV1117, TPS7A91
I have a 1.2V fixed output TLV1117LV with 3.3V in, and its output is feeding the core voltage for two FPGAs. The FPGA decoupling capacitance is ~1400 uF total.
The input slew rate is around 5V/ms, so the 3.3V input comes up in around 660 uS.
The input and output capacitors are both 1 uF.
When I put all these parameters in the Pspice model, I get a huge current spike of around 3.5A as soon as the input reaches around 2V. It stays like that until the decoupling caps are charged up to 1.2V.
When I change the input ramp to a 1 ns step the current spike gets worst. The output ramps as fast as the input, which is not realistic.
It's as if there is no current limiting at all during startup for the model. This does not seem to agree with the data sheet, and it does not agree with the results shown in your eval board documentation.
It's pretty obvious that the startup behavior of the Pspice model is off. But my questions is by how much? I'm relying on the device's current limiter to work as advertised during startup, otherwise my 3.3V power supply is going to drop out if the current demand is too high.
The model's current limiter does seem to work after the device is powered up and stable. Not so during the Vin ramp, however.
Can confirm if the current limiter will operate at start up?
Thank you