**Part Number:**LMG3411R070

Hi all

Would you mind if we ask LMG3411R070?

There is the applicaton report SNOAA15 which is "Overcurrent Protection in High-Density GaN Power Designs".

https://www.ti.com/lit/pdf/snoaa15

There is the description on the application as follows;

"During cycle-by-cycle operation, after the current reaches the upper limit with the PWM input still high,

the load current can flow through the third quadrant of the other FET of a half-bridge with no synchronous rectification.

The extra high negative voltage drop (–6 V to –8 V) from drain to source could lead to high third quadrant loss, similar to dead time loss but with much longer time.

Therefore, it is critical to design the control scheme to make sure the number of switching cycles in cycle-by-cycle mode is limited,

or to change PWM input based on the fault signal to shorten the time in third quadrant conduction mode of the power stage."

We could not understand the word "third quadrant" and "third quadrant loss".

Could you give us these meanings?

Kind regards,

Hirotaka Matsumoto