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TLV1117: Abnormal Impedance Between Input and Output

Yazhu Liu
Intellectual 1410 points
Part Number: TLV1117

Hi Team,

My customer report TLV1117-50IDCYR abnormal output issue: Vout=~10V @Vin=12V. We did following 2 verification test:

1. Impedance between input and output pin: normal device=1.08M, issue device=1k

2. If we increase or decrease input voltage, output voltage will change with it.

From above 2 phenomenon, we can make the early conclusion that there maybe some short through between input and output because of overstress.

Customer now is trying to identify the root cause, would you please some comments on the following questions? Thanks.

1. Could TLV1117-50IDCYR support application which Vin=12V, Vout=5V@20mA? Does it have minimum load requirement?

2. Datasheet suggest output capacitor to be tantalum and aluminum electrolytic with 0.2~10ohm ESR. But in customer's design, they're using 22uF ceramic capacitor. Will this lead to any potential issue?

3. Would you please share some insight about what may lead to abnormal input-output impedance issue?

Best Regards,

Livia

  • 0
    TI__Mastermind 45955 points

    Hi Livia,

    This sounds like the pass FET is damaged for these tests. Is there any possibility that there was reverse current before the test? What is the input capacitance? Sometimes if there is a large output capacitance and smaller input capacitance, during shutdown the condition VOUT > VIN can exist and cause reverse current that can damage the IC. 

    To answer the questions:

    1) Yes, Vin = 12V, Vout = 5V@20mA is supported. There is a minimum load requirement. The EC table specifies that at Vin = 15V the minimum load requirement is 5mA because the internal bias current is passed to the output. The internal bias currents increase with a larger supply, so the customer's application with Vin = 12V will have less than 5mA minimum load requirement. 

    2) This is a relic from the time before ceramic capacitors were popular. As long as the ESR requirement is met there is no issue with using ceramic output capacitors. The app note discusses this a bit:

    ESR, Stability, and the LDO Regulator

    3) See my note above. It seems that the pass FET is damaged. Otherwise, the only reason the output should follow the input is if the LDO is in dropout, but with Vin = 12V, Vout = ~10V the device should never be in dropout.

    Regards,

    Nick