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UCC5310: Higher CLAMP threshold required for isolated gate driver

Ramesh Murthy
Prodigy 60 points
Part Number: UCC5310
Other Parts Discussed in Thread: UCC27531, , UCC21710

We are planning to use isolated gate driver UCC5310MC for driving SIC mosfet with following conditions,
Switch voltage = +1KV
Switch current = 65A peak
Pulse ON period = 1us
Mosfet rise/fall time = 150ns
Pulse repetition frequency = 3Khz

We need a special requirement of +7V threshold for clamp pin activation instead of +2V to avoid false Turn ON of mosfet duting Turn OFF. So we are planning to use resistor divider circuit from Vout to CLAMP pin to activate clamp when Vout is at +7V. When Clamp is activated, Gate driver UCC27531 will be triggered as low and mosfet gate will be sinked low strongly. Whether below mentioned circuit will work properly or kindly suggest any option to have higher Clamp threshold like 5V to 7V?

/resized-image/__size/1000x500/__key/communityserver-discussions-components-files/196/3201.Capture1.JPG

  • +1
    TI__Genius 10652 points

    Ramesh, 

    What is your SiC part number?

    Are you currently seeing false turn on ?

    Is your power level >50kW? Because UCC5310 seems quite small to be used in such a high power level, especially when driving SiC. 

    The way you want to use miller clamp appears to be an alternative to just having higher drive/pulldown currents.

    Ramesh Murthy said:
    Whether below mentioned circuit will work properly

    From what I see, that circuit looks like it should work! I'm just not sure why the +7V threshold is needed. 

    at GND2+7V (you are not using negative bias), this is actually /above/ VTH of the SiCFET, so its not even fully off when you want miller clamp to be enabled. 

    Having this high miller clamp threshold might actually be worse for false-turn on performance, as it would strongly pull down gate beyond what you designed with the gate driver + gate resistor, and this directly causes higher dv/dt as part of inductive kickback (you stop current faster, you get a huge voltage spike).

    I could see an argument for using a miller clamp with a higher current rating (lower impedance path to VEE2), but not to increase its clamping threshold. .

    Please see below link, we have a really good eBook which details why miller clamp works the way it does.

    https://www.ti.com/lit/eb/slyy169/slyy169.pdf#page=23

    To me, this does not make much sense to use miller clamp in this way. I would suggest to choose a different UCC53x0 variant with higher pulldown current if that is what you need, dependent on your SiC fet parameter. I would take a look at UCC5390MC for example. 

    I also have other ideas to help with false turn off with SiC:

    * I would also suggest to look into a negative bias when driving SiC. Most SiC manufacturers will tell you that you need negative bias for their parts!

    * increase miller clamp current by connecting it to PNP. 

    * Switch to a device with higher miller clamp capability, etc, such as ISO5x5x or UCC217xx family (comparison table). 

    Best

    Dimitri

  • 0 in reply to dimitri james
    Prodigy 60 points

    Thank you for the quick response.
    We have also connected negative bias -5V at VEE2. But we have shown as GND for just not to confuse. Even after giving negative bias -5V, we have observed false turn ON problem. Kindly refer attached waveform. If 7V is threshold and refereed to -5V (VEE2) , then miller clamp will be activated when gate voltage reached to 2V (ie. 7V-5V=2V). That is why we are planning to use miller clamp option with 7V threshold.
    Our continuous power requirement is very low approx 1kW only. Actually 10 mosfets are connected in series and each mosfet is driven by individual isolated gate driver simultaneously. The switching voltage is 10KV with 1KV will be divided in each mosfet. The gate driver enable section will be optically isolated from control signal with 10KV isolation. We have observed false Turn ON even when negative bias -5V given. Kindly provide any solution to avoid false turn ON here?

    /resized-image/__size/1000x500/__key/communityserver-discussions-components-files/196/False-turn-ON-waveform.JPG

    /resized-image/__size/1000x500/__key/communityserver-discussions-components-files/196/Connection-isolated-gate-driver_2D00_miller-clamp.JPG

    Also I have query regarding Miller clamp activation. Propagation delay for miller clamp activation was mentioned as 50ns max in UCC21710. So here is an example, Turn Off command given to gate driver and gate voltage is slowly falling to 0V. Miller clamp will be trigger when gate voltage reached 2V (point A in graph), but miller clamp is still not activated and it will be waiting for propagated delay of 50ns. By the time the gate voltage would have reached 0V and started false rising due to miller effect and have reached >2V. Now the propagation delay was over, but the gate voltage is 5V(point B) and at this condition whether the miller clamp will be active and suppress the gate voltage to GND ?

    /resized-image/__size/1000x500/__key/communityserver-discussions-components-files/196/miller-clamp-function.JPG

  • 0 in reply to Ramesh Murthy
    TI__Expert 5129 points

    Hi Ramesh,

    I just wanted to let you know that Dimitri is out of the office for the next several days. He will get back to you in the middle of next week.

    Regards,

    Daniel

  • 0 in reply to Daniel Norwood
    Prodigy 60 points

    Thank you for the information. We will be waiting for the valuable solution.

  • 0 in reply to Ramesh Murthy
    TI__Guru**** 189399 points

    Hi, Ramesh,

    Let me jump in here since Dimitri is out.

    For your question about the delay of the CLAMP, you are right, I think this will cause an issue. You may want to consider using an external miller clamp that you can better tune for your unique application.

    Another thought I had is you might want to use UCC5350M since it has higher current capability, it will better control your FETs.

    Or, if you build an external miller clamp, we also have the UCC5390EC which has our highest current capability in this family.

    Best regards,

    Don

  • 0 in reply to Don Dapkus
    Prodigy 60 points

    Thank you for the response. I will check the mentioned gate driver ICS. kindly let me know whether miller clamp will be active at point B in below graph, based on that we will be planning the circuit for miller clamp.

    /resized-image/__size/1000x500/__key/communityserver-discussions-components-files/196/miller-clamp-function.JPG

    Is there any isolated Gate driver IC or any method for having variable clamp threshold ?

  • 0 in reply to Ramesh Murthy
    TI__Guru**** 189399 points

    Hi, Ramesh,

    Unfortunately, at point B, you are above the 2V threshold, and the clamp won't be active.

    We don't have anything with an adjustable clamp. That's why I was suggesting you build an external one.

    A couple other ideas for you to consider:

    Add some capacitance gate-to-source of your switch. This will act to reduce the voltage spike due to the miller capacitance. You might be able to tune it enough so our miller clamp circuitry can work correctly in your application.

    Add a pnp pull-down like discussed in this thread: https://e2e.ti.com/support/tools/simulation-hardware-system-design-tools-group/sim-hw-system-design/f/simulation-hardware-system-design-tools-forum/889128/tida-00364-explanation-of-pnp-turnoff-device-and-associated-diode

    Best regards,

    Don