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TPS61222: Background Reason of Recommended Layout

Part Number: TPS61222
Other Parts Discussed in Thread: TLV61220, TPS61220

Hi Team

I'm looking to use this TPS61222 boost converter. There is this layout guidelines where it mentions it will pose stability problems.

1. Is it possible to explain what the stability problems mean, and what will I see in terms of output? Or even better, is there some sort of calculation or relationship that can be deduced?

2. It recommends that the traces should be short and wide. Capacitors and inductors should be placed as close as possible to the IC.

a) Is it possible to explain the reason for these recommendations?

b) And how short/wide the traces should be? And how close the capacitors/inductors should be to the IC? Is there a minimum number somewhere?

 

Please help me on this. Looking forward to your reply.

thank you.

 

  • Hi Jiahui,

    Good questions! See my reply below:

    1. Is it possible to explain what the stability problems mean, and what will I see in terms of output? Or even better, is there some sort of calculation or relationship that can be deduced?

    [WW]TLV61220 uses VOUT, FB and SW to control inductor current in hysteretic mode. If the layout is bad, the noise can be coupled to those pins, thus current sensing is disturbed, which makes LSFET or HSFET prematurely shut down or turn on. VOUT sometimes cannot reach to nominal value and has low frequency oscillations.

    2. It recommends that the traces should be short and wide. Capacitors and inductors should be placed as close as possible to the IC.

    [WW]Yes, as a general recommendation. For Cin if it is placed far away from converter, loop stability may be disturbed and also transient performance is bad. Sometime if input capacitor is too far away or its capacitance is too small, UVLO circuit can be triggered. For loop stability of input L-C, see this app note.

    Analysis and Design of Input Filter for DC-DC Circuit

    COUT is very important as switching current will flow inside, it should be placed as close to IC as possible, in order to minimize FETs stress and mitigate EMI issues.

    For TPS61220, COUT, if it is too far away, can be less effective and loop can usually be unpredictable as I mentioned above,

    Inductor cannot be placed far away, the SW trace has much noise and can influence other circuitry.

    3.b) And how short/wide the traces should be? And how close the capacitors/inductors should be to the IC? Is there a minimum number somewhere?

    [WW]EVM can be a good example as a reference if you do not know how to do trace routing. How close and how much trace width usually depends on factory limitation. We recommend customer to place capacitor as close as possible, but I can see some of customers would have 1mm minimum clearance between IC and cap for hand solderability considerations. For trace, VIN and VOUT trace should be wide and solid. I would recommend use a plane for those power instead of trace. For GND, a solid GND plane as well as GND layer on layer 2 is strongly recommended for EMI and noise considerations.

    -Wenhao