Hi
What does update status register (subclass ID 82, offset 2) bits are for.
The Bit 0 and Bit 1 allow to not apply limits to changes in Qmax and Ra table when a leaning cycle is been perfomed. Is Bit 0 for Qmax changes and is Bit 1 for Ra table changes?
Bit 7 indicates if the sealed state.
What about the rest of the bits?
Regards,
Maynard
