There is a peak in the rising edge and fall edge of the driving voltage waveform when testing UCC21750-Q1. Do you know the reason? Thanks a lot
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It is hard to tell the reason without knowing more about the circuit, load, and test conditions, and waveform from other signals.
Could you please start by posting schematic of this test setup?
Though I do not reckon this is the case, please also check the stability of VEE and VDD supplies over the switchign cycle.