BQ76PL455A-Q1: FAULT_DEV[USER_CKSUM_ERR] handling

Lukasz Przenioslo

Part Number: BQ76PL455A-Q1

Hello there,

Whenever I turn on the cell balancing via CBENBL, the FAULT_DEV[USER_CKSUM_ERR] bit is being set. It seems that this is by design:

I am not interfering with CBTIME at all. Also, the mentioned bit is not always set. It also desserts itself and sets again and again. I am unable to tell what is the condition there.

I am confused on how this case should be handled by the control MCU? It seems by design, but it is still an error. What's the proper way here?

I would appreciate all help.

over 2 years ago

+1 Viktor Tasevski over 2 years ago

TI__Intellectual 2710 points

Hi Lukasz,

The reason why this is happening is because the CheckSum algorithm is continuously running in the background so changing a bit will cause a different value to be calculated and when compare to the Saved Checksum Value it will cause a fault due to unequal results.

The way that this could be handled by the MCU is that either this fault can be ignored during the cell balancing process, or the MCU can perform its own checksum calculation and compare it to the CheckSum Readout value (CSUM_RSLT register) in order to make sure that the checksum is correct.

Regards,

Viktor.

0 Lukasz Przenioslo over 2 years ago in reply to Viktor Tasevski

Expert 2630 points

Hi Viktor,

Understood, thank you for the answer. Can the IC be programmed via registers, so that FAULT_DEV[USER_CKSUM_ERR] has no influence on the nFAULT pin?

+1 Viktor Tasevski over 2 years ago in reply to Lukasz Przenioslo

TI__Intellectual 2710 points

Hi Lukasz,

Yes, you can mask the fault by setting the bit 15 (USER_CKSUM_MSK) in the MASK_DEV register (address 0x6B-0x6C).

Regards,

Viktor.

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BQ76PL455A-Q1: FAULT_DEV[USER_CKSUM_ERR] handling