Other Parts Discussed in Thread: LM25117
I am trying to simulate LM25117-Q1 based design using transient simulation model that I downloaded from the device's web site. Design is 12 to 3V3 @ 13A buck converter. LM25117 operates at 400kHz and inut voltage range is from 10V to 14V. I used Webench power designer to design the converter bu I also performed manual calculation of all the parts using datasheet formulas. Unfortunately, in both cases simulation is extremely unstable (output voltage exhibits some random oscillations), and I can't find what is wrong with a circuit. Below is simulation "cir" file content and simulation output (Voltage and inductor current).I am using PSpice for TI. Are there some known issues with LM25117 simulation model?
Regards
Goran
MAIN 3V3 POWER SUPPLY
*&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&
*NETLIST
*&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&
Rsec 200 1 0.05
Cin1 1 2 47.00u
Rcin1 2 0 1.00m
Cin2 1 3 47.00u
Rcin2 3 0 1.00m
Cin3 1 4 0.10u
Rcin3 4 0 64.00m
Ruv2 1 5 49.90k
Ruv1 5 0 13.10k
Rcomp 7 8 20.00k
Ccomp 6 7 3.30n
Chf 6 8 120.00p
Rt 9 0 12.10k
Cres 10 11 0.39u
Rcres 11 0 1.00m
Css 12 0 47.00n
XU1 0 27 6 20 0 13 8 15 17 19 0 22 10 9 12 18 5 13 26 1 0 LM25117_TRANS
* AGND CM COMP CS CSG DEMB FB HB HO LO PGND RAMP RES RT SS SW UVLO VCC VCCDIS VIN EP
* 0 27 6 20 0 13 8 15 17 19 0 22 10 9 12 18 5 13 26 1 0
Rvccdis 26 0 100.00k
Rcm 27 31 5.60k
Ccm 31 0 1.00n
Cvcc 13 14 1.00u
Rcvcc 14 0 1.00m
D1 13 15 DI_BAT54W
Cboot 15 16 470.00n
Rcboot 16 18 1.00m
XQ1 1 17 18 CSD17577Q3A
XQ2 18 19 20 CSD17575Q3
Rsens 20 0 6.00m
Rramp 18 22 54.90k
Cramp 22 23 820.00p
Rcramp 23 0 1.00m
L1 18 24 2.70u
Rl1 24 25 3.70m
Rfb2 25 8 6.04k
Rfb1 8 0 1.96k
Cout1 25 28 220.00u
Rcout1 28 0 5.00m
Cout2 25 29 220.00u
Rcout2 29 0 5.00m
Cout3 25 30 220.00u
Rcout3 30 0 5.00m
Cout4 25 32 220.00u
Rcout4 32 0 5.00m
*--------------------------
* SIGNAL SOURCE
*--------------------------
*For simulating nominal 12V input - PASSED
*V1 200 0 PWL (0us, 0) (20us, 12) (20ms, 12)
*.TRAN 20ns 8ms 0ms 20ns
*For simulating high 14V input - PASSED
*V1 200 0 PWL (0us, 0) (20us, 14) (20ms, 14)
*.TRAN 20ns 8ms 0ms 20ns
*For simulating low 10V input - PASSED
V1 200 0 PWL (0us, 0) (20us, 10) (20ms, 10)
.TRAN 20ns 8ms 0ms 20ns
*&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&
* Load
RL 25 300 1.253
XQL 300 301 0 SQJQ410EL
Vql 301 0 PWL (0us, 0) (6.5ms, 0) (6.501ms, 10) (20ms, 10)
*&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&
*--------------------------
* SIMULATION OUTPUT CONTROL
*--------------------------
.probe V(1) V(25) I(L1)
*.probe V(5) V(17) V(18) V(19) V(20) I(R6) I(L1)
*.probe V(5) V(18) V(20)
*.probe V(5) W(XQ1) W(XQ3)
*.probe W(XQ1a) W(XQ2) W(XQ4)
*.probe W(XQ1a) W(XQ3) W(XQ4)
*.probe W(XU1)
*&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&
* MODELS
*&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&
*---------------------------------------------------------------------------------------
*---------------------------------------------------------------------------------------
********************************
* Copyright: *
* Vishay Intertechnology, Inc. *
********************************
*Sep 18, 2017
*ECN S17-1461, Rev. A
*File Name: SQJQ410EL_PS.txt and SQJQ410EL_PS.lib
*This document is intended as a SPICE modeling guideline and does not
*constitute a commercial product datasheet. Designers should refer to the
*appropriate datasheet of the same number for guaranteed specification
*limits.
.SUBCKT SQJQ410EL D G S
M1 3 GX S S NMOS W= 11084220u L= 0.30u
M2 S GX S D PMOS W= 11084220u L= 0.35u
R1 D 3 2.427e-03 TC=6.044e-03,1.730e-05
CGS GX S 3.544e-09
CGD GX D 1.000e-13
RG G GY 1.92
RTCV 100 S 1e6 TC=7.020e-04,-9.630e-06
ETCV GX GY 100 200 1
ITCV S 100 1u
VTCV 200 S 1
DBD S D DBD 11084220u
**************************************************
.MODEL NMOS NMOS ( LEVEL = 3 TOX = 5e-8
+ RS = 0 KP = 1.168e-05 NSUB = 1.206e+17
+ KAPPA = 3.057e-02 NFS = 1.303e+11
+ LD = 0 IS = 0 TPG = 1 )
**************************************************
.MODEL PMOS PMOS ( LEVEL = 3 TOX = 5e-8
+NSUB = 6.937e+15 IS = 0 TPG = -1 )
**************************************************
.MODEL DBD D (
+FC = 0.1 TT = 2.000e-07 T_measured = 25 BV = 101
+RS = 1.253e-02 N = 1.094e+00 IS = 3.146e-12
+EG = 1.217e+00 XTI = 5.761e-01 TRS1 = 1.893e-03
+CJO = 4.980e-10 VJ = 1.975e+01 M = 8.909e-01 )
.ENDS
*---------------------------------------------------------------------------------------
*---------------------------------------------------------------------------------------
*---------------------------------------------------------------------------------------
*---------------------------------------------------------------------------------------
*SRC=BAT54W;DI_BAT54W;Diodes;Si; 30.0V 0.200A 5.00ns Diodes Inc. Schottky diode
.MODEL DI_BAT54W D ( IS=34.9u RS=0.210 BV=30.0 IBV=2.00u
+ CJO=13.3p M=0.333 N=2.28 TT=7.20n )
*---------------------------------------------------------------------------------------
*---------------------------------------------------------------------------------------
*---------------------------------------------------------------------------------------
*---------------------------------------------------------------------------------------
**********************************************************************
* *
* CSD17575Q3 - PSpice Model for use with OrCAD *
* *
**********************************************************************
* SUBCKT Definition: 1=D 2=G 3=S
.SUBCKT CSD17575Q3 1 2 3
* PARAMETER (local) DEFINITIONS SECTION
.param AA 3.47
.PARAM ptrc1 4.75e-3
.PARAM ptrc2 15.00e-6
.PARAM pwidthP {AA/0.8*2}
.PARAM pwidth {pwidthP*1e6}
.PARAM perimP {2.1*pwidthP}
.PARAM perim {perimP*1e6}
****** MODEL SUBCIRCUIT BEGINS HERE ******************************
M1 10 11 12 12 NMOS W={pwidthP} L=0.5u PS={perimP} PD={perimP}
DBD 8 7 DBD {AA/11.16}
CBD0 8 7 3e-12
RBD0 8 7 1e10
DDG1 10 101 DD {AA/11.16}
DDG2 11 101 DD {AA/11.16}
cgd 10 11 100e-12
* Note: gate oxide capacitance included in NMOS below
LGG 2 5 2.1e-9
cgg 5 11 1e-10
RGG 5 11 0.9
RSB 12 9 RTEMP 1.00e-6
RSS 9 8 RTEMP 1.00e-6
RSP 8 6 0.03e-6
LSS 6 3 0.47e-9
RSL 6 3 0.5
RDD 7 10 RTEMP 1.90e-3
RDP 4 7 0.05e-3
LDD 1 4 0.05e-9
*******************************************************************
.MODEL NMOS NMOS (
* CONTROL PARAMETERS
+ LEVEL = 7 VERSION = 3.2 CAPMOD = 2
* DC PARAMETERS
+ NLX = 1.74E-7 VBM = -5 DVT0 = 2.2
+ DVT1 = 0.53 DVT2 = -0.032 U0 = 550
+ UA = 3.0e-9 UB = 0.0e-19 A0 = 0.9
+ AGS = 0.0 A1 = 0.0 A2 = 0.9
+ LINT = 0.055e-6 VOFF = -0.665 NFACTOR= 1.7
+ ETA0 = 0.005 ETAB = -0.07 DSUB = 1.4
+ PCLM = 3.00 PDIBLC1= 0.02 PDIBLC2= 0.004
+ DROUT = 0.90 PSCBE1 = 3.0e8 PSCBE2 = 1e-6
+ PVAG = 0.1 DELTA = 0.0220 JS = 0
* AC AND CAPACITANCE PARAMETERS
+ CGSO = 1.00e-18 CGDO = 1e-18 CGBO = 1e-18
+ CJ = 1e-18 CJSW = 1e-18 CF = 0
* TEMPERATURE PARAMETERS
+ TNOM = 25 UTE = -1.5 KT1 = -0.80
+ KT1L = 1.0e-15 KT2 = 0.022 UA1 = -01.00e-9
+ UB1 = -0.0e-17
* PROCESS PARAMETERS
+ TOX = 3.00e-8 XJ = 3e-7 NCH = 1.435e17
+ NSUB = 1.0e16)
*******************************************************************
.MODEL DBD D (
+ CJO = 4000e-12 VJ = 1.0 M = 0.625
+ TNOM = 25 FC = 0.5 TT = 2e-09
+ XTI = 3.3 BV = 31 IS = 8.0e-11
+ N = 1.07 RS = 0.25e-3 TRS1 = 4.0e-3)
.MODEL DD D (
+ CJO = 4.00e-09 VJ = 0.4 M = 0.9
+ IS = 1e-13 RS = 0.1 TNOM = 25)
*******************************************************************
.MODEL RTEMP RES (
+ TC1 = {ptrc1} TC2 = {ptrc2})
*******************************************************************
.ENDS CSD17575Q3
*---------------------------------------------------------------------------------------
*---------------------------------------------------------------------------------------
*---------------------------------------------------------------------------------------
*---------------------------------------------------------------------------------------
**********************************************************************
* *
* CSD17577Q3A - PSpice Model for use with OrCAD *
* *
**********************************************************************
* SUBCKT Definition: 1=D 2=G 3=S
.SUBCKT CSD17577Q3A 1 2 3
* PARAMETER (local) DEFINITIONS SECTION
.param AA17570 11.16
.param AA17577 1.82
.PARAM ptrc1 4.00e-3
.PARAM ptrc2 5.00e-6
.PARAM pwidthP {AA17577/0.8*2}
.PARAM pwidth {pwidthP*1e6}
.PARAM perimP {2.1*pwidthP}
.PARAM perim {perimP*1e6}
****** MODEL SUBCIRCUIT BEGINS HERE ******************************
M1 10 11 12 12 NMOS W={pwidthP} L=0.5u PS={perimP} PD={perimP}
DBD 8 7 DBD {AA17577/AA17570}
CBD0 8 7 3e-12
RBD0 8 7 1e10
DDG1 10 101 DD {AA17577/AA17570}
DDG2 11 101 DD {AA17577/AA17570}
* Note: gate oxide capacitance included in NMOS below
LGG 2 5 2.1e-9
cgg 5 11 1e-10
RGG 5 11 1.8
RSB 12 9 RTEMP 1.00e-6
RSS 9 8 RTEMP 1.00e-6
RSP 8 6 {4.9997e-4+0.03e-6}
LSS 6 3 0.47e-9
RSL 6 3 0.5
RDD 7 10 RTEMP {0.43e-3*AA17570/AA17577+1.6e-3}
RDP 4 7 0.05e-3
LDD 1 4 0.05e-9
*******************************************************************
.MODEL NMOS NMOS (
* CONTROL PARAMETERS
+ LEVEL = 7 VERSION = 3.2 CAPMOD = 2
* DC PARAMETERS
+ NLX = 1.74E-7 VBM = -5 DVT0 = 2.2
+ DVT1 = 0.53 DVT2 = -0.032 U0 = 550
+ UA = 3.0e-9 UB = 0.0e-19 A0 = 0.9
+ AGS = 0.0 A1 = 0.0 A2 = 0.9
+ LINT = 0.055e-6 VOFF = -0.665 NFACTOR= 1.7
+ ETA0 = 0.005 ETAB = -0.07 DSUB = 1.4
+ PCLM = 3.00 PDIBLC1= 0.02 PDIBLC2= 0.004
+ DROUT = 0.90 PSCBE1 = 3.0e8 PSCBE2 = 1e-6
+ PVAG = 0.1 DELTA = 0.0220 JS = 0
* AC AND CAPACITANCE PARAMETERS
+ CGSO = 1.00e-18 CGDO = 1e-18 CGBO = 1e-18
+ CJ = 1e-18 CJSW = 1e-18 CF = 0
* TEMPERATURE PARAMETERS
+ TNOM = 25 UTE = -1.5 KT1 = -0.80
+ KT1L = 1.0e-15 KT2 = 0.022 UA1 = -01.00e-9
+ UB1 = -0.0e-17
* PROCESS PARAMETERS
+ TOX = 3.00e-8 XJ = 3e-7 NCH = 1.435e17
+ NSUB = 1.0e16)
*******************************************************************
.MODEL DBD D (CJO=3500e-12 VJ=1.0 M=0.625 TNOM=25
+ FC=0.5 TT=2e-09 XTI=3.3 BV=31
+ IS=6.0e-11 N=1.07 RS=0.25e-3 TRS1=4.0e-3)
.MODEL DD D (CJO=3.75e-09 VJ=0.7 M=0.625 IS=1e-13 RS=0.1 TNOM=25)
.MODEL DDx D (CJO=1e-09 VJ=0.9 M=0.9 IS=1e-13 RS=1.0 TNOM=25)
*******************************************************************
.MODEL RTEMP RES (TC1={ptrc1} TC2={ptrc2})
*******************************************************************
.ENDS CSD17577Q3A
*---------------------------------------------------------------------------------------
*---------------------------------------------------------------------------------------
*---------------------------------------------------------------------------------------
*---------------------------------------------------------------------------------------
.SUBCKT LM25117_TRANS AGND CM COMP CS CSG DEMB FB HB HO LO PGND RAMP RES RT
+ SS SW UVLO VCC VCCDIS VIN EP PARAMS: MODE=0
$CDNENCSTART
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$CDNENCFINISH
.ENDS LM25117_TRANS
*$
.subckt Housekeeping_UHK_S1 1 2 3 4
$CDNENCSTART
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$CDNENCFINISH
.ends Housekeeping_UHK_S1
*$
.subckt Driver_UDriver_S1 1 2 3 4
$CDNENCSTART
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$CDNENCFINISH
.ends Driver_UDriver_S1
*$
.subckt Gmiphase_UGmiphase_STrack 1 2 3 4
$CDNENCSTART
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$CDNENCFINISH
.ends Gmiphase_UGmiphase_STrack
*$
.subckt Gmiphase_UGmiphase_S2 1 2 3 4
$CDNENCSTART
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$CDNENCFINISH
.ends Gmiphase_UGmiphase_S2
*$
.subckt Clock_Gen_UClk_S1 1 2 3 4
$CDNENCSTART
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$CDNENCFINISH
.ends Clock_Gen_UClk_S1
*$
.subckt LM25117_TOPLEVEL_S1 1 2 3 4
$CDNENCSTART
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$CDNENCFINISH
.ends LM25117_TOPLEVEL_S1
*$
.SUBCKT FOR_CL_HIERARCHY Ilim_1 GEN HICCUP ILIM RES
+ HO LO VIN GND
+ VRAMP SS HICCUP_SS CLK CLK_INT
$CDNENCSTART
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.ENDS NAND2_BASIC_GEN
*$
.SUBCKT NAND3_BASIC_GEN A B C Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5
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.ENDS NAND3_BASIC_GEN
*$
.SUBCKT NAND4_BASIC_GEN A B C D Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5
$CDNENCSTART
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.ENDS NAND4_BASIC_GEN
*$
.SUBCKT OR2_BASIC_GEN A B Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5
$CDNENCSTART
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.ENDS OR2_BASIC_GEN
*$
.SUBCKT OR3_BASIC_GEN A B C Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5
$CDNENCSTART
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.ENDS OR3_BASIC_GEN
*$
.SUBCKT OR4_BASIC_GEN A B C D Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5
$CDNENCSTART
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.ENDS OR4_BASIC_GEN
*$
.SUBCKT NOR2_BASIC_GEN A B Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5
$CDNENCSTART
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$CDNENCFINISH
.ENDS NOR2_BASIC_GEN
*$
.SUBCKT NOR3_BASIC_GEN A B C Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5
$CDNENCSTART
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$CDNENCFINISH
.ENDS NOR3_BASIC_GEN
*$
.SUBCKT NOR4_BASIC_GEN A B C D Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5
$CDNENCSTART
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$CDNENCFINISH
.ENDS NOR4_BASIC_GEN
*$
.SUBCKT NOR5_BASIC_GEN A B C D E Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5
$CDNENCSTART
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$CDNENCFINISH
.ENDS NOR5_BASIC_GEN
*$
.SUBCKT NOR6_BASIC_GEN A B C D E F Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5
$CDNENCSTART
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$CDNENCFINISH
.ENDS NOR6_BASIC_GEN
*$
.SUBCKT D_D1_CL 1 2
$CDNENCSTART
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.ENDS D_D1_CL
*$
.subckt FOR_CL_S5 1 2 3 4
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.ends FOR_CL_S5
*$
.subckt FOR_CL_S6 1 2 3 4
$CDNENCSTART
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.ends FOR_CL_S6
*$
.SUBCKT INV_BASIC_GEN A Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5
$CDNENCSTART
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.ENDS INV_BASIC_GEN
*$
.model D_D1 d
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$CDNENCFINISH
*$
.SUBCKT XOR2_BASIC_GEN A B Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5
$CDNENCSTART
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.ENDS SBRBLATCHRHP_BASIC_GEN
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.SUBCKT SBRBLATCHSHP_BASIC_GEN SB RB Q QB PARAMS: VDD=1 VSS=0 VTHRESH=0.5
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$CDNENCFINISH
.ENDS DFFSR_RHPBASIC_GEN
*$
*---------------------------------------------------------------------------------------
*---------------------------------------------------------------------------------------
.END
your end.