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TPS6594-Q1: How to recover the chup from OVP status?

Lijia Zhu
Expert 3560 points
Part Number: TPS6594-Q1

Hi team,

Please check if my following understanding is correct or not:

1. The reason for OVPGDRV can be recovered after the overvoltage condition is clear is because VSYS Monitor is supplied by VSYS and it continuously monitor the VSYS, right?

2. After OVP is triggered, it is mentioned that chip will go to safety mode and a lock-up bit will be set, right? Is the bit VSYS_LOCK_EN?

3. How to recover from the safety mode(in this case: OVP is triggered)? 

4. it is mentioned in the datasheet that if VCCA stays above OVP threshold, the device will stay in SAFE RECOVERY state until supply power cycle occurs, However, when in safety mode, VINT is power down, how can I know if the VCCA is OVP is cleared or not? This part confused me a lot.

B&R

Lijia

  • 0
    TI__Genius 17835 points

    Hello Lijia,

    VSYS_DEAD_LOCK_EN = 1 is an NVM programmed device setting. When this is true and a VCCA_OVP event occurs, the device will not be able to recover unless VSYS is cycled. Even if VSYS comes back down to acceptable voltage ( 3.3V for example), the OVPGDRV will be 0 and the protection FET will be open preventing VCCA from coming up.

    If VSYS_DEAD_LOCK_EN=0, then when VCCA_OVP is cleared the the protection FET will close allowing VCCA to come up. At this point I2C communication with the PMIC will allow you to check registers.

  • 0 in reply to Michael Gambrill
    TI__Expert 3560 points

    Hi Michael,

    Thanks for the reply. 

    1. what is the default setting of  VSYS_DEAD_LOCK_EN  for TPS65941111/1212/1213?

    2. VSYS_DEAD_LOCK_EN bit is to control the dead-lock mechanism (as mentioned in the below part) enable or disable, right?

    3. when  OVP is triggered, VCCA will be 0V, all the digital part is power down, how can chip check if VSYS_DEAD_LOCK_EN  is 0 or 1?

    B&R

    Lijia

  • 0 in reply to Lijia Zhu
    TI__Genius 17835 points

    Hello Lijia,

    1. VSYS_DEAD_LOCK_EN = 1  for 1212 and 1213. Since the master PMIC is the only one monitoring VSYS using VSYS_SENSE, the value in 1111 is negligible.

    2. and 3.  This bit is not part of the customer space, it is an internal setting. It is not something that changes during operation and not be disabled.

    If in a deadlock, the system must be power cycled.