Please let me know about two points below for SPI interface clock on LP8863-Q1;
・Is there timing requirement for SCLK rise time and fall time?
・SCLK waveform on rise and fall are occur a little winding, please see below. (1V/div, and 10ns/div)
Are these winding no problem?
If problem, please let me know any countermeasure to reduce winding.
Best regards,
Satoshi
