• State TI Thinks Resolved
  • Locked Locked
  • Replies 3 replies
  • Answers 1 answer
  • Subscribers 62 subscribers
  • Views 145 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

LM25066: t2 inrush limiting timing

Jim Tsai
Expert 4470 points
Part Number: LM25066


Hi,

Could you please provide t2 time or how to calculate it, thanks.

The time is correlated to TIMER external CAP?

  • 0
    TI__Mastermind 40880 points

    Hi Jim,

    Thanks for reaching out to us.

    If the device starts directly into current limit (ILIM × VDS < PLIM), t2 can be calculated using the following equation.

    However, for most designs ILIM × VDS > PLIM so the hot swap will start in power limit and transition into current limit. In that case the estimated start time (t2) can be calculated using the following equation. 

  • 0 in reply to Avishek Pal
    TI__Expert 4470 points

    Hi Pal,

    Thanks for your prompt response.

    One more question, what is the delay time from device get EN high to output voltage start to rise?

  • 0 in reply to Jim Tsai
    TI__Mastermind 40880 points

    Hi Jim,

    CASE 1: If the insertion delay time gets over before EN becomes high, the time taken to start the output voltage rising after the EN becomes high is 8 μs + time required to charge the MOSFET gate above its threshold voltage (VGSth).


    CASE 2: If the enable becomes high before VIN crosses its POR threshold, the time taken to start the output voltage rising after the EN becomes high is time taken to cross the VIN POR threshold + Insertion Delay time + time required to charge the MOSFET gate above its threshold voltage (VGSth).


    CASE 3: If the insertion delay time doesn't get over at the instant EN becomes high, the time taken to start the output voltage rising after the EN becomes high is the remaining period of the Insertion Delay + time required to charge the MOSFET gate above its threshold voltage (VGSth).