This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

UCC21732: How to reset the fault latch of UCC21732 without risk of fireworks

Part Number: UCC21732


We have an issue with the UCC21732 transistor driver IC. Setting the combined Enable/Reset* pin low does not clear its fault latch, as we would expect. Thorough reading of the data sheet reveals that the latch is cleared at rising edge of the En/Rst* pin.

I really don't like this. It means that we must redesign the protection logic so it allows turning on a faulty converter. This may give quite spectacular results, fireworks.

* Do you have any suggestions about how to clear the fault latch without having to turn on the power transistors?

Our design is stressed on latency so we don't want to add any logic gates in the control signal paths.
A crude workaround could be to short the 5V supply. The fault handling logic could do that by turning on a large crowbar transistor briefly, so the undervoltage/powering up logic in the driver IC would clear its fault latch.

* Is this something you would recommend, does shorting the 5V rail to clear the fault latches make sense?

  • Kjell, 

    * Do you have any suggestions about how to clear the fault latch without having to turn on the power transistors?

    I am a little confused about this question. Clearing the fault latch will not turn on the power transistors unless the PWM inputs are already high. 

    If this is a concern, why not just ensure your controller keeps PWM inputs LOW after DESAT is detected?

    A crude workaround could be to short the 5V supply. The fault handling logic could do that by turning on a large crowbar transistor briefly, so the undervoltage/powering up logic in the driver IC would clear its fault latch.

    * Is this something you would recommend, does shorting the 5V rail to clear the fault latches make sense?

    This does not make sense to me, as I do not see what this accomplish differently than toggling RST/EN apart from adding complexity and cost to the design. You don't really solve any problems with RST/EN by doing that. And I am not quite sure about the problem you described with RST in your earlier point.


    In the worst case, if you had accidentally turned the FET ON back into a short circuit, DESAT detection would be tripped again, and fireworks would be unlikely to happen.

    A crude workaround could be to short the 5V supply. The fault handling logic could do that by turning on a large crowbar transistor briefly,


    Best

    Dimitri

  • In our case the PWM inputs can be at any state at any time, as these signals come straight from an analog'ish control circuit, where the two PWM inputs gives shoot through protection. Adding logic gates for enable at the PWM inputs could give the function we want, but would prefer to avoid that as these gates would add a little latency to a latency budget that is quite strained.

    The En/Rst' signal is common for several drivers so the other drivers that not in fault state will be turned on when we try to clear the fault latch.
    Desat protection would normally save the transistors, but the large current pulse can destroy something else.
    This is what we want to avoid.  The converter has already signaled that there is something wrong somewhere, so we can assume that the system is more fragile than usual.  

    Shorting the 5V supply came up as an idea for a quick and dirty workaround. It would do the same as manually cycling the power supply as we do now for clearing faults. 

    The En/Rst' pin would have done exactly what we need if the reset latch was cleared by low level and not by rising edge.

  • Kjell, 

    Perhaps you could use a buffer in front of EN/RST. 

    If that can't work, I suppose you can use the cut power method if thats the only thing that can work in your system. 

    Best

    Dimitri

  • A buffer at EN/RST' will not have any effect  here, as driving this pin is not a problem.  The way it works is the issue here. 

    Apart for putting functional change of the EN/RST pin on the wish-list for the next chip revision it seems as power cut /crowbar is the least distasteful solution.

  • Thank you for the feedback Kjell. 

    The main argument for design the fault rst on edge sensitivity is so that HIGH / LOW is treated as ONLY an enable for the device. 

    As we discussed, your solution of cutting the power to the driver would be a suitable workaround approach for FAULT reset. This is actually similar to how motor drive applications implement safe torque off. 


    Apart from this issue, are there any other questions?

    If this was it, please close the thread by pressing green button. Let us know if you have any questions in the future. 

    Best

    Dimitri