Due to the U.S. Thanksgiving holiday, please expect delayed responses during the week of 11/22.

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TPS2660: Maximum voltage level

Part Number: TPS2660

Hi Team,

Our customer is designing a PCB using the TPS26601RHFT (VQFN package) and wants to use the device on a 48V circuit. The device is rated for 60V and the spacing between the line voltage pins (such as 8, 9, 23 and 24) and other low voltage pins (such as the FLT pin 22) is on the order of .2mm. He would like to request some information on how this maximum voltage level was derived. Is there a standard to which it was tested and under what conditions (i.e. was there a specific underfill material used on the assembled device, etc.)

Regards,

Danilo

  • Hi Danilo,

    The FLT/ and UVLO pins are also rated for 60V so you can treat them as high voltage pins like IN and OUT.

    The spacing mentioned in the data sheet are physical distance and you can treat as a case with device on external PCB without any coating or underfill.

    What is the use case, EE ? and what level of clearance you are looking for ?

    Best Regards, Rakesh

  • Hi Rakesh,

    Thank you for your response. We have received this feedback from our customer.

    In our application we are trying to fuse a 48V rail using this IC. For our application we would like to have the design meet the IPC-D-275 spec. In the datasheet it states that the device is UL 2367 recognized - does the device also meet any IPC standards?

    Regards,

    Danilo

  • Hi Danilo,

    Can you share me IPC-D-275 spec to check

    Best Regards, Rakesh

  • Hello,

    the IPC-D-275 spec states that an external component lead or termination, once assembled onto a PCB without a conformal coat, should have a spacing clearance of 15 mils across a potential difference of 48V. If a conformal coat is used that spacing requirement falls to 5 mils.

    Coating this IC isn't going to be useful since it's a package with no exposed leads but perhaps underfill could be used to achieve the same result and still meet the spec.

  • Thanks for the information. 

    I see customers asking for 5mils clearance though I am not very sure how they achieve IPC clearance spec.

    You mentioned, "Coating this IC isn't going to be useful since it's a package with no exposed leads".. Sorry, I didn't get why conformal coating cannot be applied for this package ?

    Best Regards, Rakesh

  • Coating can be applied to this package but the coating material will not be able to be applied in between the pins which is where the spacing requirement is 15 mils without coating. For this we could use under-fill material which is specifically meant to penetrate into tight spaces underneath packages.

  • Thanks for the clarification.