Hi Team,
Our customer is designing a PCB using the TPS26601RHFT (VQFN package) and wants to use the device on a 48V circuit. The device is rated for 60V and the spacing between the line voltage pins (such as 8, 9, 23 and 24) and other low voltage pins (such as the FLT pin 22) is on the order of .2mm. He would like to request some information on how this maximum voltage level was derived. Is there a standard to which it was tested and under what conditions (i.e. was there a specific underfill material used on the assembled device, etc.)
Regards,
Danilo