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TPS546B24A: can't work correctly (configured by pin strap)

Part Number: TPS546B24A
Other Parts Discussed in Thread: TPS546D24A, TPS546A24A

Hello, I am using  TPS546B24A as  FPGA  core voltage supply,but it seems that  TPS546B24A  is‘t work correctly.After I  set pin 27(EN/UVLO) High, pin 1(PGD/RST_B)  remains LOW,and output voltage is shown in the figure below.

The resistance value is calculated with “TPS546D24A_TPS546B24A_TPS546A24A_ExcelCalculator_SchematicLayoutChecklist.xlsx",as shown below:

MSEL1 UP 2.37K(actual soldering 2.2K+160ohm 1%),DOWN 21.5K(actual soldering 18K+3.6K 1%);

MSEL2 UP OPEN,DOWN 10K 1%;

ADRSEL UP OPEN,DOWN 10K 1%;

VSEL UP OPEN ,DOWN 31.6K(actual soldering 30K+1.5K 1%)

Please help me find out where the problem is.The following attachment are relevant circuit and xlsx document.

Your answer will be very helpful.

6431.SCH.pdfTPS546D24A_TPS546B24A_TPS546A24A_ExcelCalculator_SchematicLayoutChecklist_20200626.xlsx   

  • Hi Shumei,

    Our US team will check it then reply you soon.

  •  

    Your first waveform set appears to show the output voltage discharging to 0.8V and then rising to 1.2V.  1.2V will trigger the over-voltage protection on the TPS546B24A when programmed for 1V output.

    It looks like there is a 100μF capacitor between VOSNS and GOSNS after the first pair of 49.9Ω resistors.  That would create a 5ms time-constant filter in the feedback path, which is more phase-shift than the loop will be able to handle.

    The first thing to try would be to remove this added filter capacitor and see if that addresses the problem.  It is likely that the added feedback sense delay is creating an instability in the output voltage and either triggering OV or OC.

    If that does not address the issue, or if it is an error in the schematic that is not present in the actual design:

    There is also a note in the schematic about "Sense point should be directly at the load capacitor placed between the sense point"

    What does the power path between the output capacitors and this load capacitor sense point look like?

    The schematic only shows 1x 470μF capacitor and 4x 100μF capacitors, but the design spreadsheet shows 4x 470μF and 12x 100μF.  Where are these additional capacitors located?

    If there is some local bypass capacitance at the converter and remote bypass capacitance close to the load with a distribution path between them, the combination of the inductance in the distribution path and the bypass capacitance at the load can form a second filter, adding to the loop phase delay and creating a loop stability issue.  The best way to address that would be to add a capacitor from the local output voltage close to the inductor / local output capacitors to the VOSNS input after the second 49.9Ω series resistor to counter the additional phase lag with local feedback.

    I would recommend starting with a 10nF capacitor, but the exact time-constant on this feedforward path will depend on the time-constant of the phase lag from the local VOUT and the remote Vout.

  • Thank you for your patience. After I removed the 100uF capacitor, the output is correct,and pin 1(PGD/RST_B)  is High.
    checked the schematic diagram repeatedly, but I didn't find this problem. This 100uF capacitor  was supposed to be 100nF.I'm too careless. Thank you again.