Hi Team,
could you please give some insight into how the two outputs of the tri-state block behave (when nSKIP is low, tri-state and high)?
BR,
Stefan
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Hi Team,
could you please give some insight into how the two outputs of the tri-state block behave (when nSKIP is low, tri-state and high)?
BR,
Stefan
Hello,
The logic functions in described in table 1 and the drive signal responding to PWM and nSKIP is clear. I understood your question is about the about the internal Tri-State Logic outputs. The outputs of the nSKIP Tri-State Logic can concluded from table 1. and the functional block diagram. There nSKIP signal is ORed with the zero crossing comparator for DRVL and is AND gated for DRVH.
Here detail explanation for nSKIP and PWM tri-state:
nSKIP |
OUTH |
OUTL |
Low |
High |
Low |
High |
High |
High |
3-state |
Low |
Low |
PWM |
OUTH |
OUTL |
Low |
Low |
High |
High |
High |
Low |
3-state |
Low |
Low |
Regards
Hi Mahmoud,
Thanks for your fast reply!
Can you maybe explain why there are two outputs?
Do they behave the same way?
BR,
Stefan
Hi Stefan,
Yes the nSKIP Tri-State logic has 2 outputs, one for upper and one for lower driver. And they behave the same way.
Regards