Hi all,
Here are 2 issues about TPS61193-Q1
- undershoot of SW
- The undershoot of SW is -0.3V in datasheet (no mention of time)the actual measurement reaches -1V in a very short time ,does this damage the IC?
- How to design the circuit to improve the problem?
- VOUT_MAX
- In datasheet, it is recommend to 1.3* maximum TFT required voltage, and what impact will it have when it's small or big?
- How to select the withstand voltage of the corresponding capacitance?
Thanks