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TPS61193-Q1: undershoot of SW and the Setting of VOUT_MAX

Part Number: TPS61193-Q1

Hi all,

Here are 2 issues about TPS61193-Q1

  • undershoot of SW 
    • The undershoot of SW is -0.3V in datasheet (no mention of time)the actual measurement reaches -1V in a very short time ,does this damage the IC?
    • How to design the circuit to improve the problem?
  •  VOUT_MAX
    • In datasheet, it is recommend to 1.3* maximum TFT required voltage, and what impact will it have when it's small or big?
    • How to select the withstand voltage of the corresponding capacitance?

Thanks

  • Hazel, 

    Undershoot of SW

    •      No. if the time slot is very short, it is ok. 
    •      Improving the PCB layout and reduce parasitic inductance LPAR1, LPAR2, LPAR3. Minimizing loop Q1, D1 and Cout. add RC snubber across Q1; 

     VOUT_MAX

    • This is to make sure there is enough room to light up LEDs. Customer should evaluate Vout_Max range to ensure LED can be lit over range 
    • A ceramic capacitor with 2 × VMAX BOOST or more voltage rating is recommended for the output capacitor

    Regards, 

    X.G