TPS65023, TPS61130 and LDOs in OMAP3517 reference design; why?

The LDOs may be connected to the output of the switching converter instead of MAIN-BAT to minimize the power dissipation in the linear regulators; this reduces the difference between Vin and Vout and therefore reduces the wasted power in the LDO.

This is typical since our switching converters have efficiency in the 90 percent range but some switch noise and linear regulators have a very clean output voltage but are inherently inefficient since any voltage drop across the LDO is burned off in heat. 

Also, the LDOs may be connected in a manner to meet the power sequencing requirements of the processor. 

You can power the LDOs directly from the 5V, just make sure the junction temperature stays below 125C and you meet the processor's sequencing requirements. 

You can also use the TPS65023 converter output to power the LDO; keep in mind though that you can have up to 300mV of dropout across each LDO. 

You should note that this evaluation platform is designed by Logic PD who have their own support forums: http://tdg.logicpd.com/

Also now that I've seen the schematic I have another explanation for why the LDOs and DCDC2 of the TPS65023 are connected to the TPS61130 and not the MAIN_BAT.
The reason for this is likely because the battery voltage can go below 3.3V (plus dropout) at which point  the TPS65023 could not output 3.3V if it were connected directly to the battery. 

Yes, the posted circuit connects the 1.8V net to the 1.8V_DPLL net once the 1.2V supply is up.