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UCC24612: Power management forum

Part Number: UCC24612
Other Parts Discussed in Thread: CSD18563Q5A, , TPS23756

Hello,

* I am using UCC24612-2 in flyback as Low-Side SR in 25W loading system, Vload = 5V.
* I found that when the flyback system with Low-Side SR working at CCM (power loading is around 23W) the SR MOSFET VDS has a high voltage spike which has exceed the rating of the MOSFET。Vgs proportional drive is 50%, Vds max spike is 75V
* The SR-MOSFET is  CSD18563Q5A (Rds on ~12mOhm) ; 
* Using eq 1 in UCC24612 datasheet,  the secondary side peak current (I load) = 4.38A, the measured minimum Rds on of SR MOSFET is 23mOhm.
* I change SR-MOSFET with larger Rds on (PSMN059-150Y,115 ; Rds on = 50mOhm), but with this new MOS, there are no proportional gate drive, hence Vds spike is much higher compare to previous MOS (133V compare to 75V)。

my question is : 
* Is my approach in dealing with Vds spike wrong? I could use snubber to dampen the  spike, but i want to make sure that i use the proper MOSFET for the design
* Did I missed something important when designing the system?
* Is UCC24612-2 suitable for flyback low side SR CCM mode (25W loading)?

* CSD18563Q5A  Vds, Vgs during CCM



* PSMN059 Vds. Vgs during CCM

thank you 

  • Hi, Ferry:

    Thank you for contacting us.

    Before the discussion, I would like share you that VDS spike is high when flyback operates in CCM operation. Proportional gate driver is helpful to speed up MOSFET turned off. The VDS is still impact by several MOSFET parameters, i.e. Qrr, softness...etc. To change a MOSFET is a fast way but please keep it in mind that the different MOSFET has different VDS performance. Sometimes you would see the higher VDSspike after you use high VDS rating MOSFET.

    Your approach is correct basically, because your waveform shows correct operation of UCC26412 with CSD18563Q5A

    It just needs to clarify some conditions based on your design. 

    * The power rating is 25W. However, your mentioned your Ipeak(load) is 4.38A. It is wired to me because the output power is only 5V*4.38A=21.9W, and Ipeak should be higher than Iout. Please check the Ipeak again. 

    * What si the Vin range? The VDS plateau is around 30V. I am not sure the input voltage. Assume this waveform is tested as 110Vac. The turn ration is around 6. If this converter is designed to 90V~264Vac. The max VDS plateau is 264V*1.414/6+5 = 65V. --> 60V MOSFET is not enough. I would suggest you to use 80V~100V MOSFET.  If it only support 90Vac~132Vac. 60V~80V should be enough.

    *UCC26412 is okay to use in CCM operation, however, CCM brings higher VDS spike, and 25W is also suitable to DCM or QR flyback. Maybe you could consider them in your next design. 

    Regards,

    Wesley Hsu

  • Hi Wesly,
    * I am sorry for the late reply, I am conducting some experiments using other SR-MOS samples.
    * Thank you for your thorough explanation, based on your explanation then re-read the datasheet I have much clearer idea on how Synchronous rectifier works.
    * Our SR-MOS selection has been resolved, thank you for you explanation.
    * I am wondering that in a ideally perfect design, what is the estimated output voltage ripple on 5V, 5A loading, the system works in CCM mode. Is there any document that you could introduce to help us improve our design。
    * Answering your question, our input voltage is 55V (POE IEEE 802.3AT), currently we are using UCC24612 with TPS23756。Due to the nature of the current loading and TPS23756 the system will work on CCM mode, hence we could not change its working characteristic into DCM。

    Thank you for your assistance,

    Regards,
    Ferry

  • Hi, Ferry:

    Thanks for your reply. I get more understand about your system specification. 

    About your question, ideally, the voltage ripple is as small as possible. However, I have to say this spec. should depend on the end system. For example, if this converter is used to charge a battery. It can pay less attention to output voltage ripple, instead, current ripple is more important to a battery.  On the other hand, if the power  is used to support a buck converter, (i.e. Vo=3.3V), high voltage ripple may cause higher duty or off time variation of buck converter which also impact end system stability and efficiency. 

    So it is hard to tell what's perfect design of the output voltage ripple, it needs to consider lots of conditions. I am sorry that I am not familiar with PoE's requirements. 50mVpeak-peak (10% of Vo) or less is good and it can not over 100mV based my experience. Also, please also consider the ambient temperature impact because capacitance might drop a lot at low temperature, which causes higher voltage ripple. 

    If you would like to know the relationship between output capacitors and voltage ripple, you may find the equation on page 7 as below.

    Isolated Continuous Conduction Mode Flyback Using the TPS55340

    Wish my sharing is helpful to you.

    Regards, 

    Wesley