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TL5209: Turning Vout On and Off

Igor Uspensky
Intellectual 670 points
Part Number: TL5209
Other Parts Discussed in Thread: AM3358

Hi,

The part has EN input that allows to enable/disable output voltage. According to the data sheet, the EN pin is CMOS-logic compatible. It'll be great if someone can clarify the following:

  • If this input is equipped with a schmitt trigger of some kind?
  • What is max. rising and falling times for the control voltage on that input?
  • If there are a known adverse effects from placing a capacitor on that input (e.g. with the purpose to slightly delay turning the LDO regulator on using a simple RC circuit)?

Thanks

  • +1
    TI__Mastermind 45635 points

    Hi Igor,

    Yes the EN input will behave like a Schmitt trigger.

    Rise and fall times of LDOs are not normally specified because they are application dependent. Startup time depends on the amount of output capacitance and how much load is connected to the output, and fall time also depends on the load and output capacitance because the load is the primary discharge path of the output capacitor. 

    There are no issues that I'm aware of with putting an RC delay on the EN pin of TL5209. This is a somewhat common way to externally add a delay to EN with other LDOs.

    Regards,

    Nick

  • 0 in reply to Nick Butts
    Intellectual 670 points

    Hi Nick,

    Thanks for the answer. That's exactly what I'd asked about.

    Now let me say something about the background for my question. Not with the venting purposes but using this occasion to remind about a long lasting problem in one of the TI-backed designs.

    TL5209 is used in the BeagleBone Black boards. There is the PMIC chip that has internal LDOs (including that for 3.3V) so TL5209 is used as an additional LDO that makes one more 3.3V source (likely with the intention to allocate more 3.3V power for the extension peripherals like SD card and capes).

    So there are two 3.3V rails in the design. One of them (3V3A) is powered by the PMIC while the other (3V3B) is powered by TL5209. According to the wiring diagram, there is a master-slave relationship between them. The PMIC is a master that decides when to turn the voltage on and off while TL5209 is a slave that all the way follows the PMIC. Clearly, the designer's assumption was that both the rails will always be turning on and off simultaneously.

    This is in fact so when the power is turning on. But when the PMIC removes power from the 3V3A rail, the 3V3B rail is still powered by TL5209. So the voltage from TL5209 gets infiltrated in the AM3358 SOC through its I/O ports and finally reaches its VDDx balls which are connected to the 3V3A rail. So the 3V3A rail effectively becoming powered by the 3V3B rail. As the EN pin of the TL5209 part is wired to the 3V3A rail, the TL5209 remains turned on despite the PMIC has stopped powering the 3V3A rail. That deadlock lasts as long as the 5V system voltage is present.

    I was very surprised on that finding because such phenomena is well known to every designer of a CMOS circuits. Even to an undergraduates. Moreover, the ad states that BeagleBone was designed in close co-operation with TI and every HW aspect was reviewed, discussed and approved. It's not clear how this resulted in a design flaw of such severity. Anyway BeagleBone is by no mean a new design so I've done some research and have found that the problem is known to the public for years and a lots of related discussions can be found on this forum and elsewhere. It's long time mentioned in the outstanding issue list at the design maintainer's github page.

    This year, the maintainers has released C3 revision of BeagleBone Black design. Some minor problems are fixed but not this issue, which is of severity one in my opinion. So every new customer is faced to the housekeeping task to fix the board in one way or another before putting it to any usage (to avoid subjecting the SOC to unnecessary electrical stress on each power off event).

    A number of possible hardware fixes were proposed during the discussions. For each of them, the obvious requirement is to remove direct connection of the EN pin to the 3V3A rail. Fortunately, it's not a problem because TL5209 is a big part so it's easy to lift the pin. Next, a circuit is required that will control the EN pin as appropriate. In general, every circuit is consuming power so my desire is to minimize that additional consumption but to drive the EN pin hard enough in order to eliminate the risk of catching a noise from the nearby traces. From that point, the output impedance of the controlling circuit shall be low (the lower the better). Unfortunately, the only way to achieve that when power is removed is to connect the EN pin to ground with a low Ohm resistor. But that will cause to wasting of power when the pin is driven high. Not a good idea. IMHO the better way would be to use a resistor of higher value and a small capacitor in parallel, which will increase noise immunity (at the cost of introduction of some delay which is not desired in that case).

    That's why I'd asked about the switching characteristics of the EN pin. A strange question but similarly strange use case just should not be there.

    Again, thanks for the clarification, Nick.

    ---

    regards,

    Igor