This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TPS65381A-Q1: The external FET for VDD1 is too hot, is there any solution?

Part Number: TPS65381A-Q1
Other Parts Discussed in Thread: TPS62150A-Q1, TPS62130A-Q1

Hi experts:

As you known TPS65381A-Q1 is qualified to power TMS570 family of processor. As recommended design, the VDD1 output from TPS65381A-Q1 is used to power the VCC power rail of TMS570, which is 1.2V/510mA(typ), 990mA(max). VDD1 is a linear regulator with external pass FET which generate 1.2Vout from 6V input. Such the power dissipation of external FET is very high, 2.4W to 4.8W. This high power dissipation is very difficult for customer to handle. I am wondered is there any solution to reduce the power dissipation of VDD1? such as replacing VDD1 linear regulator with discrete buck DC/DC?

Thank you!

John

  • Hi John,

    I would recommend ensuring the customer has a very large, solid ground plane to help dissipate heat from the FET. Given the high current consumption of their design it may not fully resolve their issue, but it should help to provide some additional thermal dissipation.

    A small DC/DC can be sure in place of the core regulator and supplied directly from VDD6 (for example TPS62130A-Q1 or TPS62150A-Q1) with the output of the DC/DC being connected to the VDD1_SENSE pin so that TPS65381A-Q1 can continue to monitor the core voltage.

    Best regards,

    Layne J

  • Hi Layne,

    Thank you so much for reply.

    Yes, your proposal is a good solution. But there are several questions: 1. how to control the power up/down sequence of VDD6? 2. If VDD1_SENSE connected to DC/DC output, that means the VDD1 LDO will work in open loop condition, i am not sure if the internal monitor circuit can cntinue monitor VDD1?

    Thank you!

    John

  • Hi John,

    VDD6 powers up based on the input power supply and wakeup pins of the PMIC (IGN and CANWU). To sequence the descrete core regulator I would recommend connecting VDD3/5 or VDD5 to the enable pin of the regulator so the core rail is sequenced slightly after the other power supplies connected to VDD6.

    I can confirm that using the VDD1_SENSE pin with an external regulator works. You will still need to use the resistor dividers on the sense pin to set the output voltage but the voltage monitor will work the same as if VDD1 was in use.

    Best regards,

    Layne J