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TPS65381A-Q1: Regarding Internal clock signal and Q&A mode Watchdog Time equation

Part Number: TPS65381A-Q1

Good day, 

I'm kihun kim from HL klemove south korea.  

We have used this part since 2012 for automotive steering application. 

But I wondering that why some datasheet description change compare with before. 

So I want to check below to clearify watchdog concept. 

If you available, could you please answer until 11/9? 

Our customer wants to clarity below questions. 

1. Reagrding Internal clock signal (f sysclk), below data sheet mean MCU(master) must using watchdog timer including deviation +/-5%? 

   Our design team confuse that this clock signal only use reulator(slave) watchdog function. 

2. Compare to Y2012 vs Y2017 data sheet, Equation has been changed as below. 

    Are these same equation? 

    If yes, Please explain detail how these are same. 

    If not, Please explain why this equation concept change. 

   Before(2012) :

                        

   After(2017) : 

                      

3. The reason why watchdog sequence concept change.  

  Before(2012) : Answer 3,2,1 must in window 1 time by sequenc / Answer 0 must in window 2 time. 

                        

  After(2017) :  Answer 3,2,1 in window 1 or 2 time / Answer 0 must in window 2 time.  

                       

   

  • Hi Kihun,

    1. That statement means that the timing for the watchdog inside of the device is run off of the internal +/-5% clock, not an external clock.

    2. We changed these equations in the datasheet because we found the new equations better reflect the actual device behavior. The new equations reflect the need for digital synchronization as well as the idea of window sizes.

    3. This change does not have any impact for a system that worked under the original text of the datasheet. This allows some additional flexibility for timing the watchdog answers based on how the device functions but again will not have any impact on a system working under the original requirement.

    Best regards,

    Layne J

  • Hi Layne J,

    Thank you for your prompt response. 

    Could you please check below additional questions? 

    Q1. When we set up register to use watchdog function, Should we need to applying +/-5% clock signal deviation in window time equation(MCU side)? 

          In 2012 data sheet window time equation, there has no window time min/max value. 

          If clock signal +/-5% must be applicable, we must apply for clock signal +/-5% in equation?   

    Q2. That mean these 2 equations are different? 

           If yes, Don't we need to any change setting value like MCU wathcdog resgister and so on... 

           Additionally, could you please check any similar case in other customer?

  • Hi Kihun,

    Please expect an update by EOD tomorrow

    Thanks,

    Daniel W

  • Hi Kevin,

    It is important to no longer consider the older versions of the datasheet. Once a PCN has been sent out and the datasheet has been updated only the new version should be used to understand and use the device. 

    In the new equations there are 0.95 and 1.05 terms included in the minimum and maximum equations which account fore the +/-5% clock error.

    I cannot say if you will need to change any settings in your system/on your MCU, you will need to determine if your system settings match the requirements found in the new datasheet versions. As long as the timing designed into your system meets the requirements of the datasheet there should not be any issues.

    Best regards,

    Layne J