Good day,
I'm kihun kim from HL klemove south korea.
We have used this part since 2012 for automotive steering application.
But I wondering that why some datasheet description change compare with before.
So I want to check below to clearify watchdog concept.
If you available, could you please answer until 11/9?
Our customer wants to clarity below questions.
1. Reagrding Internal clock signal (f sysclk), below data sheet mean MCU(master) must using watchdog timer including deviation +/-5%?
Our design team confuse that this clock signal only use reulator(slave) watchdog function.
2. Compare to Y2012 vs Y2017 data sheet, Equation has been changed as below.
Are these same equation?
If yes, Please explain detail how these are same.
If not, Please explain why this equation concept change.
Before(2012) :
After(2017) :
3. The reason why watchdog sequence concept change.
Before(2012) : Answer 3,2,1 must in window 1 time by sequenc / Answer 0 must in window 2 time.
After(2017) : Answer 3,2,1 in window 1 or 2 time / Answer 0 must in window 2 time.