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[FAQ] Powering FPGAs which require large input capacitance

How to ensure loop stability for our devices when powering FPGAs which require large input capacitance typically? 

  • Typically, in our datasheets we have a recommended maximum output capacitance for every device. To power FPGA rails with input capacitance in the range of 600-800uF, this becomes a challenge. The very high distributed capacitance down the rail could potentially lead to loop stability issues. Therefore; it is recommended to perform loop stability measurements for our device in individual applications.
    The best alternative would be the TPS54x18 family. Devices with external compensation have more flexibility and can support larger Cout. However, the solution size will be much larger.