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BQ77915: HIBERNATE Mode entry conditions

Part Number: BQ77915

The data sheet (Rev. I) chapter 9.3.5 says: "When the PRES pin is left floating (...), the load is not connected, and the device is not in any fault condition, the device enters HIBERNATE mode after tPRES_DEG_ENT time."

However in no additional conditions for HIBERNATE mode entry are mentioned. Figure 9-15 also suggests that the device will enter hibernate mode from normal and fault modes 4.5 seconds after letting PRES floating.

My tests with BQ77915EVM also show the latter behaviour: About 4.5 s after I remove the shunt from J4, BQ77915 goes into hibernation (no voltage at AVDD) regardless of the previous situation. Any connected load is shut down.

For my application the forced hibernation observed with BQ77915EVM is beneficial/required.
Is it just a confusion in the data sheet or is the intended behaviour the one described in 9.3.5? If 9.3.5 is correct, do I have a defective device and may the behaviour of BQ77915 be adjusted in the future?

  • Hello Lasse,

    Can you please describe how you are testing and measuring this? If there is no voltage at VDD, are there no batteries connected? What fault conditions are active when you remove the shunt to induce HIBERNATION? What's the voltage at the LD pin?

    HIBERNATION mode will turn off the FETs, so the batteries would be disconnected from the load, causing the load to shut-down. That sounds normal.

    The description of 9.3.5 should be accurate.

    Best Regards,

    Luis Hernandez Salomon

  • Hello Luis,

    thanks for your reply.

    There is voltage at VDD all the time. I use the 3S setup as shown in Figure 3 of the EVM data sheet. The absence of the 3V at AVDD is used as an indicator for the device being in hibernation.

    Additionally there is a load resistor with a mechanical switch connected between PACK+ and PACK-. LD seems to behave as expected: With the load enabled, LD is low in normal operation and goes high when a fault shuts down the load. With the load disabled LD is low.

    I tried UV, OV, OTD and UTD so far. In all cases the device goes into hibernation after removing the shunt.

    As I understood 9.3.5, I thought the device would prevent hibernation in case of current flowing (e.g. by using the state comparator logic). If the LD pin is used, a fault would be required anyway for the load detection to be active (according to

  • Hello Lasse,

    I will check with others in the team.  But I do believe this confusion may be due to a mistake/inconsistency of the datasheet. 

    I will follow-up soon.

    Best Regards,

    Luis Hernandez Salomon

  • Hello Lasse,

    Just to update you, we believe this is an inconsistency in the datasheet. I will submit this to get this fixed.

    Follow the behavior that you observed, and seen in Figure 9-15.

    I apologize for the confusion.

    Best Regards,
    Luis Hernandez Salomon

  • Thanks for your investigation Luis,

    that is good to hear since I prefer the Figure 9-15 behaviour.

    Best Regards