Other Parts Discussed in Thread: TPS3851
Hi team,
I am trying to implement the UCC2946 in a logic circuit which requires the usage of a watchdog timer and a reset signal. However, I am having some troubles with the pinout configuration of this device, because for the moment I have not been able yet to emulate the performance described in the datasheet.
What I am trying is to make the component output a constant HIGH level at WDO\ as long as the input WDI is been toggled periodically with a square pulse. In addition I am using the RST\ signal to assert a single LOW pulse during startup so as to initialize the logical components in the circuit, then RST\ is just kept as HIGH and is not used again.
Currently I have managed to achieve this RST\ behaviour, but the problem is that I find impossible to make the WDO\ go low: it will stay HIGH no matter the input at WDI, when I am expecting to go into constant LOW as soon as WDI stops getting toggled.
The current pinout being used is the following:
RP: A 160 nF capacitor from the pin to GND
RTH: 3.3V
WP: A 100 uF capacitor from the pin to GND
WDI: A periodic signal toggled from a microprocessor
WDO\ and RST\ are redirected to other components of the circuit without further additions.
How should the UCC2946 be connected so as to achieve the desired performance (lowering WDO\ as far as WDI is not toggled)?
Thanks,
Macarena