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UCC2946: WDO not going low after WDI stops toggling

Part Number: UCC2946
Other Parts Discussed in Thread: TPS3851

Hi team,

I am trying to implement the UCC2946 in a logic circuit which requires the usage of a watchdog timer and a reset signal. However, I am having some troubles with the pinout configuration of this device, because for the moment I have not been able yet to emulate the performance described in the datasheet.

What I am trying is to make the component output a constant HIGH level at WDO\ as long as the input WDI is been toggled periodically with a square pulse. In addition I am using the RST\ signal to assert a single LOW pulse during startup so as to initialize the logical components in the circuit, then RST\ is just kept as HIGH and is not used again.

Currently I have managed to achieve this RST\ behaviour, but the problem is that I find impossible to make the WDO\ go low: it will stay HIGH no matter the input at WDI, when I am expecting to go into constant LOW as soon as WDI stops getting toggled.

The current pinout being used is the following:

RP: A 160 nF capacitor from the pin to GND

RTH: 3.3V

WP: A 100 uF capacitor from the pin to GND

WDI: A periodic signal toggled from a microprocessor

WDO\ and RST\ are redirected to other components of the circuit without further additions.

How should the UCC2946 be connected so as to achieve the desired performance (lowering WDO\ as far as WDI is not toggled)?

Thanks,

Macarena

  • Hello Macarena,

    I would like to reconfirm the WP pin capacitance value. Is it really 100uF? The capacitor is too large. The device will need long time for the capacitor to charge and discharge to perform correct WD operation.

    With WP = 100uF, the tWP (Watchdog monitoring time) will be equal to 2500 sec. This may be reason for WD output not going low.

    May I know what time period you need for WD monitoring? We may have to scale the WP capacitor accordingly. 

    Based on your need, we can suggest an alternate as well.

    Thanks & Regards,

    Shridhar.

  • Hi sir, thanks for your rapid response.

    Effectively, I just confused "nano" with "micro", I was aiming at a 100nF capacitor which could lead to a period of 2.5 sec, so as to be big enough to see the changes in the component's behaviour while testing it.

    Even though, I have just checked lowering the capacitors, changing both to 18 nF, which should be providing tWP=450 ms; and tRP=56.25 ms. I do not have actually any strict requirement about timing: in my application the reaction should be as rapid as possible (less than a second), but there are no limiting constraints. I have observed that even by changing these capacitors to 18nF WDO\ stays HIGH, even at startup when WDI has not started to be toggled. It justs outputs 3.3V always.

    Is the pinout configuration I am using correct? If so, is there any alternate setup of the component that could achieve my needs?

    Thanks,

    Macarena

  • Hello Macarena,

    The behavior you report is not expected.

    Please share following details

    1. Schematic for the device external connections.

    2. Please check the waveform on the WP pin. The capacitor should show rising and falling voltage curves. Please share the waveform you observe.

    3. Please confirm if the behavior is observed across UCC2946 devices or only one device is showing the unexpected behavior.

    If you need independent RESET and WDO outputs, I can recommend TPS3851 as an alternate solution.

    Thanks & Regards,

    Shridhar.

  • Hi, currently I am testing the device alone, with no other connections rather than the ones specified in the following schematic:

    I have observed the waveform at WP: surprisingly, there is no falling or rising edge detected, it stays as a constant 0. May I leave it unconnected, or connect it to a pull-up resistor to Vdd, as advised for TPS3851?

    This behaviour has been the same for a pair of components I have been able to test, however I am expecting to receive some more within a few days, with a different package-type which could ease testing the component as I am doing.

    Thanks,

    Macarena

  • Hello Macarena,

    Please check if the capacitor C30 has a short across it. It may restrict the capacitor charging and discharging behavior and the voltage will stay 0.

    If a short exists, we need to remove that.

    If you do not notice a short, please replace C30 with 1Mohm resistance. With internal 400nA current drive, we should observe 0.4V across resistance. This will ensure the internal current source working.

    These experiments will help confirm if this is a device issue or external component/connection issue.

    TPS3851 has different internal architecture. External connections of TPS3851 will not work as is with UCC2946. I recommended TPS3851 as another solution from TI.

    Thanks & Regards,

    Shridhar.

  • Hi, 

    Checking the capacitor C30 I have noticed that when WDI is been toggled it stays at 0, it is when the toggling stops when the waveform shows the capacitor charging and discharging, as follows:

    I have also tried to substitute the capacitor with a 1 Mohm resistor, following your suggestion. Voltage measured at the resistor shows 0V, so the expected 0.4V drop is not being achieved.

    May the performance of this pin cause the continuous WDO\=1?

    Thanks,

    Macarena

  • Hello Macarena,

    With 18nF capacitor, the watchdog time period is 450msec. If the WDI pin does not receive any valid transition for 450msec, the WDO\ will go low. During this 450msec period, the WP signal will rise (to 1.235 V) and fall (to 100mV) 8 times. Once the cap charge discharge occurs 8 times continuously, the WDO\ will be driven LOW

    The capacitor charge discharge behavior will be observed when WDI signal is toggling provided we have enough time between consecutive pulses. Else the WP capacitor will not be charged and will stay low.

    With the existing setup, please check for following waveform and share for further study. Use following settings

    CH1 = WP pin, CH2 = WDI, CH3 = WDO\

    Use time base as 100 msec per division.

    Voltage scale as 1V per division.

    Experiment 1:-

    1. Toggle WDI at 250msec interval i.e Frequency of 2Hz

    2. Trigger the with WDI rising edge.

    3. Capture oscilloscope plot for 3 channel simultaneously.

    Expectation - WDO\ will stay HIGH always. WP pin should show toggling behavior. The levels should reach 1.235V at it's peak.

    Experiment 2:-

    1. Do not toggle WDI pin. Stay HIGH or LOW

    2. Trigger scope on CH1 (WP pin) with 1V level

    3. Capture oscilloscope plot for 3 channel simultaneously.

    Expectation - WDO\ should go low, after 8 rising and falling transitions on WP pin. Once WDO\ is low, WP pin should stay low until next WDI transition.

    Please share these waveforms for understanding of device behavior.

    Thanks & Regards,

    Shridhar

  • Hi sir, I have performed the suggested experiments, coming up with the following result:

    In the experiment 1 (first image), the capacitor shows the described charging and uncharging behaviour, WDO appears to be toggling in accordance to WDI.

    In the experiment 2 (second image), I have tested WDI as a constant high signal. The capacitor shows its respective charging-discharging cycles, also WDO starts as high and gets low right after eight cycles (as expected).

    Thanks,

    Macarena

  • Hello Macarena,

    The second experiment results show that WDO\ goes low as expected when no toggling done on WDI input after 8 cycles for capacitor charge and discharge. This meets your requirement.

    Experiment 1 results are unexpected. The WDO\ should not follow WDI input. Some how the capacitor is in the 8th cycle. I did not expect this. May be an issue with capacitor time base calculation.

    Can we repeat experiment 1 with increasing the WDI frequency by 2x?

    I expect the WDO\ will stay high even when WDI is toggling.

    This will be correct device behavior.

    Thanks & Regards,

    Shridhar.

  • Hi, with regards to experiment 1 I have repeated the test doubling the frequency of the signal. Results (first image) show the capacitor charging and discharging 8 times, however, WDO still follows WDI even without the complete sequence of 8 capacitor cycles.

    To discard the possibility of being WDO somehow shorted to WDI (because initially I thought that this behaviour could be origined by a short between both pins, or by accidentally measuring WDI instead of WDO, explaining why both signals perform equally) I conducted the same experiment but with a sinusoidal wave (same frequency, 4 Hz). Results (second image) show that WDO does not exactly follow WDI, as in this case maintains the sequence of high-low transitions according to the rising edges of the WDI signal.

    What did you mean by the capacitor time base calculation? Isn't the capacitor expected to guarantee a 450ms watchdog period, provided that it is of 18nF? How could be the capacitor causing the misbehave of the component?

    Thanks,

    Macarena

  • Hi, observing the performance of the capacitor and thinking about the "time between pulses" you suggested initially, I started to wonder whether the issue could be related to the configuration of the WDI signal.

    I performed an experiment by using a modulable PWM signal instead of the "standard" square pulse I had been using. For an initially given frequency of 4 Hz, I started to increase the duty cycle of the signal in order to reduce the time that WDI is at a low level. For my surprise, it was exactly at a pulse width of 240 ms when WDO started to stay as a continous high, and the capacitor showed constant charged/discharge cycles between pulses. However, the peak of the capacitor's voltage does not reach the expected 1.25 level, could this be acceptable provided that the overall performance of the component (in these conditions) meets my requirements?

    I repeated this test varying the frequency and pulse width of each signal, coming to the conclusion that WDO starts to behave as expected from a duty cycle of exactly 96%. The frequencies, experimentally-determined minimum pulse width values and its associated duty cycle is shown in this table:

    Frequency (Hz) Period (ms) Minimum PW (ms) Duty Cycle
    4 250 240 96,00%
    8 125 120 96,00%
    16 62,5 60 96,00%
    32 31,25 30 96,00%

    To support this experiment, here are two images of it: the first one shows how WDO and WP behave with a constant PWM signal with a 96% duty cycle. The second waveform captures the behaviour of these signals when WDI is being toggled continuously as in the first image but suddenly is stopped. It can be observed that once WDI is cut the capacitor performs the exact set of 8 charge/discharge cycles, after which WDO finally reaches the low level.

    May this solution be suitable and secure, or should I try with another configuration?

    Thanks,

    Macarena

  • Hello Macarena,

    Thanks for sharing additional details of experiments with duty cycle.

    The device is behaving as expected and this should work for your application.

    I was under the impression that any duty cycle should work. I learned something new about this device today.

    No other experiments needed. You can use the device with duty cycled operation implementation.

    Thanks & Regards,

    Shridhar