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TPS7A90: Soft-Start Timing without Cns/ss

Part Number: TPS7A90

I understand from Figure 36, and the text in the DS how the soft-start system works.

I understand how to use Equation (5) to calculate the "tss" value (soft-start time)

The equation suggests with C_NSSS = 0nF, that soft-start time = 0[s]
Does this indicate that, after the propagation delay from V_EN going HIGH, the output rise-time is completely dependent on load conditions, and no "soft-start" feature is active?

Looking at Fig. 32~35, it seems there is propagation delay from V_EN going HIGH, to VOUT starting to rise.
Looking closer at the graphs, the propagation delay seems related to C_NSSS.
A higher I_NSSS current, or a lower C_NSSS value, has a "quicker" propagation delay. (Fig. 32 = ~80us delay)
But a lower I_NSSS current, or a higher C_NSSS value, has a "longer" propagation delay. (Fig. 33 = ~400us delay)

How is the propagation delay defined? It seems this will affect the calculated "tss" value, and could throw off any system-critical timings...


  • Hello Darren,

                         Yes, if the Noise reduction/Soft Start Capacitor is not used then the soft start feature is not active. I am not sure I completely understand your analysis in Q2. Please note that the charging current used in Fig. 32 and Fig. 33 are the same (since SS_CTRL pin is connected to GND). Since no CNR/SS is used in Fig. 32, the ramp up time for Vout is minimal and as a result the propagation delay (delay between VEN and VOUT reaching nominal value) is small. Fig. 33 on the other hand uses CNR/SS = 10nF, as a result it has soft start and a larger ramp up time for Vout and larger propagation delay. Hope this was of help. Let us know if you more questions. Thanks!



  • Hi Srikanth,

    I made a PPT describing my question.

    Left Image = No Soft-startup (no C_nsss cap)
    Right Image = Soft-startup (10nF C_nsss cap)

    There is this "delay" before the output starts rising, and the time for this delay is not defined in the datasheet.
    Could you provide some clarification on this?

    Figure 32 from DS shows ~80us delay before output starts rising (no soft-start, so sharp rise)
    Figure 33 from DS shows ~400us delay before output starts rising (soft-start, so voltage rise is more gradual)

    I don't understand the clarification between these delay changes.


  • Hello Darren,

                         Figures 33, 34, and 35 suggest that the Reference voltage needs to reach ~200mV before the Error Amplifier becomes fully operational, and only then the output begins to rise. In Figure 32, there is no external Soft Start Capacitor connected, hence the current source very quickly charges up the internal capacitor (which is in the order of 10's pF) and hence the reference voltage very quickly rises to 200mV, activating the Error Amp and hence the output waveform also begins to rise in very short time (~100uSec). In figure 33, an external Soft Start capacitor of 10nF is used, which requires a larger time to charge up using the same current source, hence the it takes longer for the reference voltage to charge to 200mV and the Error Amp to turn on, only after which Vout begins to rise. Hence it takes ~450uS for the Output to start rising. I hope I was better able to explain my answer. Let me know if you have any more questions. Thanks!