I am using TPS62125DSGR in my design which has 12 V at input voltage and 'Sensor_en' as the enable signal coming from FPGA. The ideal output at the output of TPS62125DSGR should be 2.82V. This 2.82 V is given to a LDO AP2202K-ADJTRG1 (Diodes Incorporated) which lowers it to 1.8V (VDD).
The problem I am having is when 'sensor_en' is high, then the voltage measured at LDO output comes out to be correct, i.e 1.8V, but when the 'sensor_en' is low then the voltage measured at the LDO output measures 1.4V, which ideally should be 0. Can you please look at the attached schematic page and tell how can that be possible,