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UCC21540: UCC21540DWR's VDDB High level voltage spec

Part Number: UCC21540

Hi Team,

There is a good new that we  DIN UCC21540DWR

And there have one thing need your support,

The customer asked the datasheet about the Low level with -0.5V to -2V maintenance  200ns! But High level does not have a SPEC for how long of +0.5V to 2V can be maintained.

Does High level could endure +0.5V to 2V maintenance 200ns? THX

  • Hello Kygo,

    Thank you for reaching out on E2E. As you mentioned, UCC21540 can withstand -2V on the OUT pins for 200ns, but maximum voltage is only rated at 0.5V + VDD regardless of the duration. So it is not recommended to allow any voltage above VDD + 0.5V, for any amount of time. 

    If this answers your question please let us know by clicking the green button, otherwise let us know how we can continue to help.



    *Please note that responses on E2E may be delayed this week due to holidays in the US*

  • Hi Daniel

    Like this measured wave !
    Do we have the opportunity to provide Guarantee mail, because the spike lasted a short time. THX

  • Hi Kygo,

    Due to the US holiday we will be OOO until Monday(11/29), so please expect delayed responses.

    I will let Daniel comment on what we could tell the customer judging from the waveform you sent, but in the meantime could you confirm with the customer how they were probing the signal and if they're confident the waveform is an accurate representation of the signal?

    Using a large probing loop could cause the overshoot captured on the oscilloscope to be larger than the actual signal feeding into the gate driver. The customer should use a small probing loop (can use a pig tail like the image below), should use scope highest sampling rate, and probe max bandwidth to get accurate measurements.

    Best regards,

    Andy Robles

  • Hello Kygo,

    We are not able to guarantee any performance beyond the specifications of the datasheet.  

    As Andy mentioned, the first step should be to confirm that this is not a probing artifact by making sure best practices are used when probing, as described by Andy.

    If the spike is determined to be real, then there are two things to adjust to keep the output voltage within the specified limits. The first is to reduce the inductance in the gate path, which is likely hard to do. The second option is to increase the gate resistance, choosing a value as described here: This allows the output waveform to be tuned such that it stays within the datasheet specifications.

    Please let us know if this answers your question by clicking the green button, or let us know how we can help further.