• State TI Thinks Resolved
  • Locked Locked
  • Replies 1 reply
  • Answers 1 answer
  • Subscribers 62 subscribers
  • Views 81 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TPS7B82-Q1: VOUT when EN is held low

Gokul Koraganji
Mastermind 19150 points
Part Number: TPS7B82-Q1

What will be the VOUT when EN is held low?

Is the VOUT floating or driven 0?

If it is driven, what is the pull down resistance?

We are using this LDO for ethernet PHY DP83TC812, where we are trying to cut-off power supplies using EN of the LDO, but the supply is not going to 0V. It is saturating mid rail at around 1.5V.
We want to understand if this is a board level issue or whether LDO is floating.

Please refer to the image below, VDDA is the output of the LDO, INH is the signal connected to EN

  • 0
    TI__Genius 12511 points

    Hi Gokul,

    As you've seen, there is no internal fast pulldown resistance. However there are Feedback resistors, which will discharge the output capacitor at no load causing Vout to reach 0V, but they are high resistance to limit leakage current, so they are not very fast, the load will do so faster. It is not strictly floating, there are pathways to ground, but it is not rapidly driven to 0V either.

    There must be something else on the board that is pulling that voltage high, as you can see the output flatline at 1.9V then step up to around 2.1V and hold. The LDO at this point is off, and the internal FET is high impedance. The output rail is only draining through the internal FB resistors at this state of operation, and is not being sourced from the LDO, so something else is pulling the output high.

    Regards,

    John