This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

[FAQ] UCC21520: How can I prevent false turn on of the Power FET during powerup?

Part Number: UCC21520

How can I prevent false turn on of the Power FET during powerup?

  • In applications where the gate to drain capacitance is high as compared to the gate to source capacitance and high dv/dt is experienced during power up, current through the gate drain capacitor has the potential to cause false turn-on in the power FET. Normally, the internal driver clamp prevents this from happening, but in systems with particularly severe conditions this current can push the limits of the internal driver clamp, even causing false turn-on. While this is not a problem in most circuits there are some scenarios, such as when the power transistor has a very large Cgd, that require an external clamping circuit.

    Why This Happens

    When the gate driver is first powering up it is common for the switch node voltage to already be changing, often because the low side transistor is already switching. This change in switch node voltage translates to fast dvdt across the high side power transistor, causing current to flow through the miller capacitor of the transistor, Cgd. This is shown in Figure 1. When the ratio of miller capacitance to Cgs is large, this current needs another path, flowing through the gate resistance and into the driver. This causes a voltage differential both across Rgate, and within the driver, potentially raising the gate voltage enough to turn the power transistor on. While drivers often have internal clamp circuitry to prevent this false turn-on, systems with high dvdt across the power transistors or with large miller capacitance, can induce currents too large for the internal clamp to handle.

    Figure 1: Parasitic Capacitance

    Prevention of False Turn On

    To prevent the possibility of this false turn on an external clamping circuit can be implemented as shown in Figure 2. This circuit adds a diode and BJT to provide a strong pulldown when the driver is off, clamping any current that could otherwise turn on the power transistor. The effect of this clamp can be seen in Figure 3, with the blue waveform showing Driver_OUT voltage, and the Red waveform showing voltage at the gate of Q2. The dashed lines are without the Q3 clamping circuit, and the solid lines are with the extra clamp. 

    Figure 2

    Figure 3

    References & additional resources