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[FAQ] TPS62933: How to achieve single-layer PCB layout with improved EMI?

Part Number: TPS62933
Other Parts Discussed in Thread: TPS54302, , TPS54335A

A single layer printed circuit board (PCB) is widely used in major appliances, residential air conditioners, home audios, speakers and other small home appliances. Compared to multi-layer, single-layer PCB is easy to build with effective cost and shorter production cycle. Easy to use and BOM cost effective is valued in home appliances and smart applications, where an engineer wants to achieve a single layer printed circuit board (PCB) layout.

Most engineers follow the golden rule for PCB layout: place input capacitors as close as possible to the IC and make the current loop formed by input capacitors, VIN pin and GND pin as small as possible to reduce noise and EMI.

Figure1 Critical Current Loop

In devices with a conventional pin-out, the SW/PH pin is usually located between the VIN and GND pins. Therefore, in order to shorten the distance between CIN and IC, it is necessary to change the PH/SW pin trace not to hinder the connection of CIN and IC. We could achieve that with moving the PH/SW trace to the bottom layer or using several 0-ohm resistors to jump traces. However, double-layer PCB cost is much higher than singe-layer PCB and adding 0-ohm resistors will increase BOM cost.

Optimized pin-out allows engineers to place input capacitors close enough to IC without moving the PH/SW to the bottom layer or using 0-ohm resistors. Figure 2 provides the “SW” location in conventional Pin-out and Optimized Pin-out respectively.

Figure 2 conventional pin-out vs optimized pin-out

Take TPS62933, 3.8-V to 30-V, 3-A synchronous buck converter with optimized pin-out, as an example to show how to achieve single-layer PCB. Figure 3 shows the comparison among EVM reference designs of TPS62933, TPS54335A and TPS54302. It is obvious that TPS62933 could achieve single-layer layout easily, meanwhile the EVM reference design of TPS62933 has the smallest PCB solution size and doesn’t need any VIAs or bottom layer to routing. What’s more, TPS62933 is of great EMI performance and robustness. the optimized pin-out reduces the critical current loop area which mitigate their own noise and improve EMI performance.

Figure 3: Critical Current Loop Comparison of TPS62933, TPS54335A and TPS54302

Figure 4, 5 and 6 separately demonstrate the EVM schematic, reference PCB layout and BOM (with solution size) of TPS62933, and illustrate how to achieve the single-layer PCB layout. More detailed layout guidelines can be found in datasheet.

Figure 4 The EVM Schematic of TPS62933

Figure 5 The Reference PCB Layout of TPS62933

Components

Part number

Size (mm^2)

IC

TPS62933, SOT583

1.6mm * 2.1mm

Inductor

74439346068, Würth Elektronik

6.65mm * 6.45mm

Input capacitor

CGA5L1X7R1H106K160AC, TDK, 1206 package

3.2mm * 1.6mm, 2x

Output capacitor

C3216X5R1V226M160AC, TDK, 1206 package

3.2mm * 1.6mm, 2x

Other components

0603 package

1.6mm * 0.8mm, 10x

Total size (mm^2)

Including components and trace space

22mm * 20.3mm = 446.6mm^2

FOM (mA/mm^2)

TPS62933 max loading is 3A

6.717 mA/mm^2

Figure 6 Solution Size Summary

In conclusion, optimized pin-out buck converter can help you conveniently achieve single-layer PCB layout with improved EMI.