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UCD3138128A: I2C interface questions on two-stage slope on SCL signal

Part Number: UCD3138128A
Other Parts Discussed in Thread: UCD3138A

Hi Champ,

I am asking for my customer. They are using UCD3138128A as the slave. 

We measured that there are two-stage slope on the rise time of SCL signal, the waveform is shown as below pic. (no added I2C buffer)

Though, currently the data is receiving all correctly.

The customer would still have a concern of causing problems in the interpretation of the data. Is there a slight possibility that it caused a communication error?

Also, what makes it there are two-stage slope ? How to effectively find the root cause of it ?

I suppose the issue relates to the customer's hardware, is there any other possibility ?

Thanks for any reply.

Best Regard.

  • Is there always a two stage slope, or does it only happen sometimes?

    What value of pull up resistor are they using?  

    We recommend using around 700 ohms to make sure that the signal is pulled up correctly regardless of capacitance or other issues.  

  • Hi Ian,

    The SCL signal rise time always happens all the time when receiving data.

    I suggested a smaller resistor for pull-up resistor already (currently using 1k Ohm) since the two-stage SCL signal is still there.

    On more question from the customer.

    How does the PMBus/I2C module get its value on UCD3138128A?

    Since it has a clear declaration on other MCU TRM about all the incoming bits are sampled with the rising edge of the clock(SCL) line.

    Would you please indicate which part of the SPEC that mentions the relevant information in UCD31xx Digital Power Supply Controller TRM ? 

    Thanks for your any comment.

  • Johnny, by receiving  data do you mean when the controller is reading data from the UCD3138A?

    We don't specify when we sample the data.  We just specify that we meet the timings on the PMBus as shown in the data sheet.  

    There's no real point to specifying if we receive data on the rising edge of the clock, because if the data changes during the clock high time, it will be interpreted as a stop or start, which will corrupt the message.  

  • Hi Ian,

    Yes, the controller is reading data from the UCD3138128A.

    I am clear what you are saying, thanks.

    The reason why I am asking is because the competitor has declared clearly that the level should be below 0.2Vdd or above 0.8Vdd, which is the logical level that GPIO can recognize, and it is unknown in between.

    Correspond to our datasheet, the screenshot below should have the same same interpretation, correct ?

    The level should be below 1.1 V or above 2.1V, which is the logical level that GPIO can be recognized, and it is unknown in between, correct ?

    Thanks and regards.

    Johnny

  • It is possible to see a double slope rise time with UCD devices when reading from them.  What you say about the voltage levels is true, but, of course, the signal must go between the 2 levels, and it does not do so instantaneously.  There is a rise time spec in the SMBus spec, which defines the AC characteristics for the PMBus.  If the rise time meets the SMBus spec, and the signals meet the other timing requirements, it should work correctly.  Otherwise it may be necessary to decrease the terminating resistor value.