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UCC21520-Q1: UCC21520-Q1 Bootstrap Capacitor design

Part Number: UCC21520-Q1
Other Parts Discussed in Thread: TIDA-01604

Dear E2E design support,

Hello, I'm Kihoon Kim from Seoul National University of Science and Technology, South Korea.

Now I'm designing gate drive circuit for 2-phase interleaved totem-pole PFC using UCC21520-Q1 (Bootstrap gate driver).

I referred ref design TIDA-01604, which is same topology and similar power rating as mine.

But I have a question.

At low frequency leg which is switching 50Hz, is Bootstrap capacitance 4.7uF enough?

I calculated a fomula, the requirement is 50uF at least.

How do you think?

Thank you.

Best regards.

  • Ki Hoon, 

    My colleague is currently working on this query and should reply soon, no later than monday. 

    Best

    Dimitri

  • Hi Ki Hoon,

    Can you tell me a few details about your design to help me make an accurate recommendation?

    What is the switch gate charge 'Qg' of your FET?

    What is the VDD supply voltage?

    How much dead time do you have set?

    What is your bootstrap diode's forward voltage drop?

    I am following this bootstrap guide here: https://www.ti.com/lit/an/slua887/slua887.pdf

    Regards,

    Krystian

  • Krystian,

    Qg is 31nC, VDD is 20V,

    dead time is 10ns.

    And also forward voltage drop is 0.71V.

    I will follow your guide.

    Thank you.

    Best regards.

  • Hi Ki Hoon,

    Thanks for the information. I will update you with my calculations today.

    Regards,

    Krystian

  • Ki Hoon,

    The largest contributor to the boot capacitance value is the acceptable VDD ripple based on the requirements you gave. A small VDD ripple, like 0.2V for example will mean that you will have to use a very large capacitance to store charge long enough for such a low switching frequency, over 80uF. If your VDD ripple was higher, like 1V, you could use a smaller capacitance like 33uF. If the VDD ripple is too high, you could trigger the UVLO of the driver or if the gate of the FET requires consistent voltage, then inconsistent VDD can lead to inconsistent performance. You could use a larger capacitor to reduce the VDD ripple, but the tradeoff is that it will take more cycles to charge the VDDA capacitor all the way, making your startup delay longer. 

    Alternatively, you could increase the switching frequency which would have a massive impact on reducing your boot capacitance size or use a separate isolated power supply al together. 

    Regards,

    Krystian