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UCC24612: Risk of shot-torugh during SR MOSFET turning off

Part Number: UCC24612

Hi Team,

My customer uses UCC24612-2 for SR MOSFET control in PFC cirucit, and he finds a short period of VGS overlaping under CCM, just as the pictures show below.

Will this be a risk of shot-through on high/low side MOSFETs? Is it possbile to add some dead time between SR FET turn-off and main MOSFET turn-on? 

CH1: PFC main MOSFET VGS

CH2: SR MOSFET VGS

  • Hi, Charles:

    Would you please share the schematic and provide Vg, VDS and IDS wave as 1st figure?

    Regards,

    Wesley

  • Hi, Charles:

    And what's test condition of figure 1 and figure 2 since the DRV is different? and it may need to zoom in more to check the miller plateau of each MOSFET. 

    Regards,

    Wesley

  • Hi Wesley,

    Please refer to the waveforms below, thanks.

    CH1: SR Vgs ; CH2:SR Vds ; CH3:Main MOS Vgs ; CH4:SR Ids

    Regards,

    Charles

  • Hi, Charles:

    The VDS voltage is 100V. I think it is a boost, not PFC. Am I right?

    In CCM sync boost topology, the low side MOSFET needs to be turned on first and then the high side VDS polarity changed. So the gate must be overlap for a short time.  Based on the waveform your share, the IDS does not show short-through phenomenon, the waveform is okay. However, the VG duration is not stable here. It means the VD has noise to turn off VG much earlier. It may make higher conduction loss. It could be improved by layout to reduce the impact by stray inductance. 

    What's the MOSFET that customer used as high/low side?  To reduce Rg of discharging path of high side MOSFET and to increase Rg of charging path of low side MOSFET is a way to make this condition safer.

    Regards, 

    Wesley