UCC28070: Single phase operation

Hello Oba, 

Thank you for your interest in the UCC28070 PFC controller. 

I will also differ a little bit from other advice, but I will try to be clear on my reasons.
My main assumption: for this application, your customer will always use single-phase only; no intention to design in 2 phases for future use and de-populate phase-B for this use. 

1.  I recommend to leave GDB pin unconnected (floating).  Reason: an open pin avoids any unnecessary power loss if the gate-drive voltage goes high for any reason. GDB is expected to stay LOW (see next step), but if for any reason GDB goes high each cycle, then a resistor or capacitor termination will be a power loss.  But I intend for GDB to stay LOW. 

2.  I recommend to connect CAOB to GND.  Reason: From the block diagram on page 13 of the datasheet, you can see that the GDB driver is gated by an S-R flip-flop.  A "CLKB" pulse would drive GDB high, but the flip-flop is Set-dominant, so a "1" on S will keep GDB off.  The PWM ramps at comparator PWM2 start at a slight offset from GND, so connecting CAOB to GND will force PWM2 output to always be HIGH because the PWM ramp will always be higher voltage than CAOB.  This should keep GDB off.

3.  I recommend to connect CSB to GND.  Reason: it puts the output "OutB" of the current-synthesizer block into a known state. OutB will be 0V.  Even though it doesn't matter what happens at CSB when CAOB is GNDed, it seems like a good practice to me to avoid the possibility of noise stress on the CSB input.  A resistor from CSB to GND can also be used, but the resistor is unnecessary clutter and cost when directly GNDing CSB accomplishes the same thing. 

Additional considerations: 

When CSB is GNDed, the IMO voltage will always be higher than OutB, so CA2 will try to drive an output current.  The transconductance gain is 100uA/V but CA2 has a current limit of 50uA.  So there will be a constant bias power loss of 50uA x VCC.  If VCC = 12V, then extra Pbias = 0.6mW.  

The design equations of the Detailed Design Procedure in Section 8.2.2 (starting page 30) are all based on interleaving 2 phases, where 1/2 of the total power goes through each phase.  Several of the equations must be modified to account for all power going through only 1 phase.  These are Equations 41, 43 , 44, 45, and 47. 
For eqn 41, peak to peak ripple current ΔIL must be chosen much smaller than suggested in the text, because there is no interleaving to reduce the net ripple.  If ΔIL is too high, the inductor will run in DCM and input current harmonic distortion will go up significantly.  Choose ΔIL to keep inductor current in CCM at the lightest load (at high line) where iTHD is important. 

Also, several equations involved with the interleaving must be modified.  With no interleaving, equation 2 is not applicable, only eqn 1 for high frequency ripple in Cout.    Eqn 18 & 19 must have the "1/2" factor removed.  There may be some other equations somewhere in the datasheet that I might have missed, so I recommend that you read through it to verify that all places where interleaving makes a difference have been identified. 

Regards,
Ulrich