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LM74610-Q1: Request a schematic review (LM74610-Q1)

Part Number: LM74610-Q1
Other Parts Discussed in Thread: CSD18513Q5A

There is a request for a schematic review from a customer.

- The input reverse polarity protection circuit is configured by applying LM74610-Q1. (Case 1.)

- Use 2 motor drivers (DRV8244S-Q1) (input: 4.5 ~ 40Vdc, current peak: 21A)

[Schematic attached]

Schematics-1.pdf

Q1) Is there any part to be corrected in the circuit diagram? Please review.

Q2) Instead of configuring the CAP at the input terminal at once, I added the CAP to the driver input terminal (C247, C248), is there any problem? If there is a problem, please suggest an alternative solution.

Please check. Thank you.

  • Hi Grady,

    I can help you with the schematic review of LM74610-Q1. Please provide the following information,

    1. What is the voltage on VBAT rail ? (both positive and negative(reverse polarity condition))
    2. What is the max load current flowing through the path of Q201 ?
    3. What is the part number of Q201 ?

    For schematic review of DRV8244S-Q1, please post a separate query on e2e with the part number mentioned as DRV8244S-Q1.

  • Hi, Praveen

    I will answer you below.

    1. For both positive and negative polarity, VBAT has a voltage range of 9-24V.
    2. The maximum load current of Q201 is 40A peak, and the normal value is about 20A.
    3. The part number of Q201 is CSD18513Q5A, and it is a TI product.

    Q1) Is there any part to be corrected in the circuit diagram? Please review.

    Q2) Instead of configuring the CAP at the input terminal at once, I added the CAP to the driver input terminal (C247, C248), is there any problem? If there is a problem, please suggest an alternative solution.

    Please check. Thank you.

  • Hi Grady,

    Please see my response below,

    Q1) Is there any part to be corrected in the circuit diagram? Please review.

    The only problem I see here is the FET Rds(on). The LM74610-Q1 can provide up to 5V of gate to source voltage (VGS). The max Rds(on) at room temp. would be 5.3 mohms and it can increase with temperature.  Customer will have to consider the power loss in the FET and check if the thermals of FET would be within acceptable limits. We generally recommend the FET junction temp. to be operated at less than 100C in steady state and Max. ambient temp. 

    Considering the load current and Rds(on) in this case, it looks like the power loss and thermals are going to be high. Customer can consider using multiple FETs in parallel or select a FET with lower Rds(on).

    Q2) Instead of configuring the CAP at the input terminal at once, I added the CAP to the driver input terminal (C247, C248), is there any problem? If there is a problem, please suggest an alternative solution.

    With respect to LM74610-Q1, the placement of C247, C248 is not relevant. You can take this decision depending on the the system level or DRV8244S-Q1 requirements.